This is manually squashed with a change to import dv_base_reg too, a
new module that was created by Weicai's "csr backdoor support" patch.
It's needed because it is a dependency of dv_lib.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
c91b50f357a76dae2ada104e397f6a91f72a33da
* [prim_ram*_adv] Update core files and add prim_util dependency
(Michael Schaffner)
* [prim_ram*_adv] Implement Byte parity in prim_ram*_adv (Michael
Schaffner)
* [dvsim] Run tests in "interleaved" order (Rupert Swarbrick)
* [dvsim] Remove unnecessary getattr/setattr calls from SimCfg.py
(Rupert Swarbrick)
* [dv] Add support for multiple ral models (Srikrishna Iyer)
* [rtl] Fix prim flash dependency (Srikrishna Iyer)
* [prim_fifo_sync] Make FIFO output zero when empty (Noah Moroze)
* [dv] csr backdoor support (Weicai Yang)
* [prim] Add a "clog2 width" function (Philipp Wagner)
* [dvsim] Allow max-parallel to be set in the environment (Rupert
Swarbrick)
* [dvsim] Fix --reseed argument (Rupert Swarbrick)
* [prim_ram/rom*_adv] Break out into individual core files (Michael
Schaffner)
* [prim_rom] Align port naming with prim_ram* (Michael Schaffner)
* [dv] Allow a test to have "simple" timestamps (Rupert Swarbrick)
* [dvsim] Improve --help message (Rupert Swarbrick)
* [dvsim] Remove unused --local argument (Rupert Swarbrick)
* [dvsim] Small tidy-ups to mode selection in SimCfg.py (Rupert
Swarbrick)
* [fpv] formal compile fix required by VC Formal (Cindy Chen)
* [dvsim] Fix error detection logic in Deploy.py (Rupert Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This commit was generated by running
for hj in $(grep -l opentitan vendor/*.vendor.hjson); do
$opentitan/util/vendor.py -U -c $hj
done
and then squashing together all the resulting commits. It will be
followed by a patch that combines these vendor.hjson files (using the
vendor tool's new "mapping" functionality), but we need a patch first
to get everything in sync before squashing together.
Individual commit messages below:
*****
Update common_ifs to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/common_ifs in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] This fixes a padctrl reset issue in the chip level tb (Michael
Schaffner)
*****
Update csr_utils to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/csr_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] csr_excl_item printed msg cleanup (Srikrishna Iyer)
* [dv] Fix top-level mem test (Weicai Yang)
* [doc] Fix typo in CSR exclusions (Michael Schaffner)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)
*****
Update dv_lib to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/dv_lib in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv/chip] fix csr_hw_reset X assertion issue (Cindy Chen)
* [dv] Use phase_ready_to_end to handle end of test (Weicai Yang)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)
*****
Update dv_utils to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/dv_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [dv] Add begin...end around if statement in macro (Weicai Yang)
* [dv] Fix timeout due to too many non-blocking TL accesses (Weicai
Yang)
* [spi_device/dv] Add interrupt seq (Weicai Yang)
*****
Update dvsim to lowRISC/opentitan@249b4c31
Update code from subdir util/dvsim in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dvsim] Enable round-trip of env variables into log (Philipp Wagner)
* [dvsim] Support for running pre-built SW tests (Srikrishna Iyer)
* [dvsim] Print what cmd is executed in the log (Srikrishna Iyer)
* [dvsim] Specify encoding of opened files as UTF-8 (Philipp Wagner)
* [dvsim] Simplify factory methods for FlowCfg (Rupert Swarbrick)
* [dvsim] small fix on css style (Cindy Chen)
* [dvsim] support css format for email (Cindy Chen)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)
*****
Update uvmdvgen to lowRISC/opentitan@249b4c31
Update code from subdir util/uvmdvgen in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [uvmdvgen] Minor env gen fix (Srikrishna Iyer)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)
* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [uvmdvgen] Automate checklist gen, fixes (Srikrishna Iyer)
* [doc] Unify dashboard, manual spec table (Srikrishna Iyer)
* [dvsim] Added fusesoc generator for RAL (Srikrishna Iyer)
