Rupert Swarbrick
f35a407906
Update lowrisc_ip to lowRISC/opentitan@5cae0cf1
...
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
5cae0cf1fac783e0d0df8c8597bf65322a696a56
* Allow different assertion "backends" in prim_assert.sv (Rupert
Swarbrick)
* [prim_prince/doc] Update documentation (Michael Schaffner)
* [prim_prince] Add option to instantiate a registers half-way
(Michael Schaffner)
* [prim_cipher_pkg] Reuse sbox4_8bit to build wider sbox layers
(Michael Schaffner)
* [dv/prim] add PRESENT testbench (Udi Jonnalagadda)
* [uvmdvgen] Scoreboard update. (Srikrishna Iyer)
* [flash_ctrl dv] Fix V1 tests (Srikrishna Iyer)
* [prim_cipher_pkg] Replicate common subfunctions for other widths
(Michael Schaffner)
* [prim/present] fix PRESENT decryption bugs (Udi Jonnalagadda)
* [prim/present] fix some PRESENT encryption bugs (Udi Jonnalagadda)
* [dv] Add get_mem DPI function to Verilator simutil (Stefan
Wallentowitz)
* [lint/entropy_src] Add the entropy source to the lint regression
(Michael Schaffner)
* [style-lint] Fix some common style lint warnings (Michael Schaffner)
* first set of security checks added to D2 checklist (Scott Johnson)
* [fpv/tooling] add FPV class extension in dvsim (Cindy Chen)
* [dvsim/lint] Minor fixes for printout issues and result parser
status (Michael Schaffner)
* [syn] Print detailed messages to .md if publication is disabled
(Michael Schaffner)
* [prim_util] Do not use $clog2() in Xcelium (Philipp Wagner)
* [prim] Update ResetValue parameter in prim_flop_2sync (Timothy Chen)
* Modified some command-line arguments for DSim (Aimee Sutton)
* [prim_util] Make prim_util a package (Philipp Wagner)
* [dv] Move mem checking to scb (Weicai Yang)
* [lint] Make PINCONNECTEMPTY Verilator waiver common (Philipp Wagner)
* [prim] - Fix generic flash enum reference (Timothy Chen)
* [prim_ram_*adv] Mark cfg port as unused (Philipp Wagner)
* [prim_fifo_sync] Use vbits() for simpler code (Philipp Wagner)
* [prim_flash] Add reset to held_part (Eunchan Kim)
* [lint] Add more lint waivers (Philipp Wagner)
* [dv] Add random backdoor for csr_hw_reset (Weicai Yang)
* [dv] Add set_freq_khz in clk_rst_if (Weicai Yang)
* [prim] Close GAPI file handle in primgen (Philipp Wagner)
* [fpv/prim_packer] fix CI failure due to index out of bound (Cindy
Chen)
* [prim_arbiter_*] Propagate parameter changes (Michael Schaffner)
* [prim_arbiter_tree] Fix incorrect arbitration behavior (Michael
Schaffner)
* [prim_arbiter_ppc] Add more FPV fairness checks (Michael Schaffner)
* [prim_ram*] Add an assertion that checks wmask consistency (Michael
Schaffner)
* [memutil] Increase max memory width to 256bit (Tom Roberts)
* [flash] - Add flash info page support (Timothy Chen)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
2020-07-01 14:54:13 +01:00
Rupert Swarbrick
8c11bd780c
Update lowrisc_ip to lowRISC/opentitan@c91b50f3
...
This is manually squashed with a change to import dv_base_reg too, a
new module that was created by Weicai's "csr backdoor support" patch.
It's needed because it is a dependency of dv_lib.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
c91b50f357a76dae2ada104e397f6a91f72a33da
* [prim_ram*_adv] Update core files and add prim_util dependency
(Michael Schaffner)
* [prim_ram*_adv] Implement Byte parity in prim_ram*_adv (Michael
Schaffner)
* [dvsim] Run tests in "interleaved" order (Rupert Swarbrick)
* [dvsim] Remove unnecessary getattr/setattr calls from SimCfg.py
(Rupert Swarbrick)
* [dv] Add support for multiple ral models (Srikrishna Iyer)
* [rtl] Fix prim flash dependency (Srikrishna Iyer)
* [prim_fifo_sync] Make FIFO output zero when empty (Noah Moroze)
* [dv] csr backdoor support (Weicai Yang)
* [prim] Add a "clog2 width" function (Philipp Wagner)
* [dvsim] Allow max-parallel to be set in the environment (Rupert
Swarbrick)
* [dvsim] Fix --reseed argument (Rupert Swarbrick)
* [prim_ram/rom*_adv] Break out into individual core files (Michael
Schaffner)
* [prim_rom] Align port naming with prim_ram* (Michael Schaffner)
* [dv] Allow a test to have "simple" timestamps (Rupert Swarbrick)
* [dvsim] Improve --help message (Rupert Swarbrick)
* [dvsim] Remove unused --local argument (Rupert Swarbrick)
* [dvsim] Small tidy-ups to mode selection in SimCfg.py (Rupert
Swarbrick)
* [fpv] formal compile fix required by VC Formal (Cindy Chen)
* [dvsim] Fix error detection logic in Deploy.py (Rupert Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
2020-06-12 16:15:11 +01:00
Rupert Swarbrick
640a868293
Update lowrisc_ip to lowRISC/opentitan@d78da129
...
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
d78da129c7f2b115ccabd1c3af199e0e5812f365
* [dv] Fix loop when waiting for end of run phase in dv_base_monitor
(Rupert Swarbrick)
* [util] Remove docgen references (Tobias Wölfel)
* [dvsim] Small tidy-ups in dvsim.py command line parsing (Rupert
Swarbrick)
* [dvsim] Tidy up wave dumping logic (Rupert Swarbrick)
* [dv/xbar] Add chip-level xbar support (Weicai Yang)
* [prim] Fix lint errors (Pirmin Vogel)
* [prim] Rework how primgen.py writes out parameter lists for
instantiations (Pirmin Vogel)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
2020-06-04 16:26:43 +01:00
Rupert Swarbrick
6a557b47ee
Update dvsim to lowRISC/opentitan@1d17b122
...
Update code from subdir util/dvsim in upstream repository
https://github.com/lowRISC/opentitan to revision
1d17b1225d324c81da522c69317335a83edd5ddb
* [dvsim] PEP8 fixes in dvsim (Rupert Swarbrick)
* [dvsim] Fix PEP8 error and slightly tidy code in testplan_utils.py
(Rupert Swarbrick)
* [dvsim] Correct bug in regression creation in dvsim's Modes.py
(Rupert Swarbrick)
* [dv] Enable xcelium coverage publish (Weicai Yang)
* [tool/dvsim] Enable Xcelium coverage and clean up email arg (Cindy
Chen)
* [dv] add send email option to dvsim.py (Cindy Chen)
* [util/dvsim] Convert time to UTC timezone (Eunchan Kim)
* [dvsim] Fix broken link of xbar testplan (Weicai Yang)
* [dvsim] Add CTRL-C support (Weicai Yang)
* [dvsim] Initial verible lint integration (Michael Schaffner)
* [dvsim] Add control of max job submission per second (Weicai Yang)
* [dv/tool] Add support to choose sub-cfgs (Cindy Chen)
* [dvsim] Enable coverage collection with Xcelium (Srikrishna Iyer)
* [dvsim] Update lint flow due to changes in synthesis (Michael
Schaffner)
* [dvsim] Synthesis target integration (Michael Schaffner)
* [dvsim] Added fusesoc generator for RAL (Srikrishna Iyer)
* [dvsim] Fix summary table (Greg Chadwick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
2020-04-28 17:42:02 +01:00
udinator
f69c6fbabd
[dv] initial icache testbench ( #711 )
...
* [dv] add vendor .hjson files for dv tools
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* Update common_ifs to lowRISC/opentitan@0d7f7ac7
Update code from subdir hw/dv/sv/common_ifs in upstream repository
https://github.com/lowRISC/opentitan to revision
0d7f7ac755d4e00811257027dd814edb2afca050
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* Update csr_utils to lowRISC/opentitan@0d7f7ac7
Update code from subdir hw/dv/sv/csr_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
0d7f7ac755d4e00811257027dd814edb2afca050
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* Update dv_lib to lowRISC/opentitan@0d7f7ac7
Update code from subdir hw/dv/sv/dv_lib in upstream repository
https://github.com/lowRISC/opentitan to revision
0d7f7ac755d4e00811257027dd814edb2afca050
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* Update dvsim to lowRISC/opentitan@0d7f7ac7
Update code from subdir util/dvsim in upstream repository
https://github.com/lowRISC/opentitan to revision
0d7f7ac755d4e00811257027dd814edb2afca050
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* Update uvmdvgen to lowRISC/opentitan@0d7f7ac7
Update code from subdir util/uvmdvgen in upstream repository
https://github.com/lowRISC/opentitan to revision
0d7f7ac755d4e00811257027dd814edb2afca050
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* Update dv_utils to lowRISC/opentitan@0d7f7ac7
Update code from subdir hw/dv/sv/dv_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
0d7f7ac755d4e00811257027dd814edb2afca050
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* [dv] initial icache testbench
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* [dv] add top_pkg and its core file to icache/dv
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* [dv] update ibex_core and ibex_icache corefile dependencies
Signed-off-by: Udi Jonnalagadda <udij@google.com>
* [dv] add .vpd support for wave-dumping
Signed-off-by: Udi Jonnalagadda <udij@google.com>
2020-03-27 11:02:47 -07:00
