Commit graph

73 commits

Author SHA1 Message Date
udinator
1e8381bfa1 Update google_riscv-dv to google/riscv-dv@4450592 (#347)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 44505927a70a6234b996d15f2e51bd1e2632b68e

* Dump performance counters to testbench at EOT (Udi)
* Fix a constraint issue (google/riscv-dv#174) (taoliug)
* Allow split a long test to small batches (google/riscv-dv#173)
  (taoliug)
* Fix ius compile problem (google/riscv-dv#172) (taoliug)
* Add basic functional coverage for RV64IMC (google/riscv-dv#171)
  (taoliug)
* Initial prototype of functional coverage (google/riscv-dv#169)
  (taoliug)
2019-09-23 18:08:16 -07:00
udinator
2f120d4ade
Update google_riscv-dv to google/riscv-dv@80d4294 (#333)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 80d429475138b4b94d863030246a06980c89889d

* Fix mstatus randomization issue (google/riscv-dv#168) (taoliug)
* Lower the percentage of JAL instruction (google/riscv-dv#167)
  (taoliug)
* Add an option to run a directed assembly test with ISS
  (google/riscv-dv#166) (taoliug)
* Add memory fault handlers (Udi)
2019-09-18 14:13:03 -07:00
udinator
2c71a26680
Update google_riscv-dv to google/riscv-dv@0d2b5b7 (#321)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0d2b5b7b8b1cdbce74d9e123a427052b12accd7b

* Add user extension support (google/riscv-dv#163) (taoliug)
* Update README (google/riscv-dv#162) (taoliug)
* Fix compilation issue (google/riscv-dv#161) (taoliug)
* Fix compilation issue (google/riscv-dv#160) (taoliug)
* Adding dsim support (google/riscv-dv#159) (taoliug)
* Fix RV64A typo (google/riscv-dv#158) (taoliug)
2019-09-16 13:43:35 -07:00
udinator
3fcf5a634d
Update google_riscv-dv to google/riscv-dv@c98d89c (#312)
Update code from upstream repository https://github.com/google/riscv-
dv to revision c98d89cdff7b56d9911904e05e6b46e005233280

* Interrupt test integration (Udi)
* Update README for illegal/hint instruction (google/riscv-dv#155)
  (taoliug)
* Refactor illegal/hint instruction generation (google/riscv-dv#154)
  (taoliug)
* Skip x0 in GPR save/restore (google/riscv-dv#153) (taoliug)
* Move user_define.h to the beginning of the program (google/riscv-
  dv#151) (taoliug)
* Add user_define.h (google/riscv-dv#149) (taoliug)
* Move instr_bin to a separate section (google/riscv-dv#148) (taoliug)
* Remove temp files (google/riscv-dv#145) (taoliug)
* Move dv_defines.svh outside the package (google/riscv-dv#144)
  (taoliug)
* Fix typo (google/riscv-dv#141) (taoliug)
* Refactored loop instruction stream, reduce global reserved registers
  (google/riscv-dv#139) (taoliug)
* Remove obsolete sample program (google/riscv-dv#138) (taoliug)
* Update readme (google/riscv-dv#137) (taoliug)
* Skip kernel instruction/data pages when not needed (google/riscv-
  dv#136) (taoliug)
* Re-organize data page generation (google/riscv-dv#135) (taoliug)
* Re-organize text and data section (google/riscv-dv#134) (taoliug)
* Refine the bare program mode (google/riscv-dv#133) (taoliug)
* Add a bare program mode (google/riscv-dv#130) (taoliug)
* Allow running riscv-dv from other directories (google/riscv-dv#128)
  (taoliug)
* Fix trace compare issue (google/riscv-dv#123) (taoliug)
* Optimize for constraint solving performance (google/riscv-dv#122)
  (taoliug)
* Avoid ISS simulation timeout (google/riscv-dv#121) (taoliug)
* Optimize irun randomization performance (google/riscv-dv#120)
  (taoliug)
* fix ius compile/simulation warnings (Tao Liu)
* Fix ius compilation failure (Tao Liu)
* Fix google/riscv-dv#109 ius constraint solver failure (Tao Liu)
* Add ebreak sequence generation and cmdline options (Udi)
* Added dret instruction to random generation (Udi)
* Tighten up regex in spike log tracer. (Dave Estes)
* Fix generation of debug handshake (Udi)
* Fix wfi generation, add indent to core_initialization handshake
  (Udi)
2019-09-13 14:34:56 -07:00
taoliug
6a88d1ed03
Update google_riscv-dv to 102791d (#266)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 102791dbb7eb992d3bc22336d2e4e5f0d688e761

* Merge pull request #104 from google/flow (taoliug)
* Remove debug print (Tao Liu)
* Merge pull request #103 from google/flow (taoliug)
* Improve randomization performance (Tao Liu)
* Merge pull request #102 from udinator/debug (taoliug)
* Prevent x0 from being used as load adress register (Udi)
2019-08-27 11:23:31 -07:00
udinator
ce8be4f2fd
Update google_riscv-dv to google/riscv-dv@faddfa4 (#263)
Update code from upstream repository https://github.com/google/riscv-
dv to revision faddfa49f456f3f8ef8c4231865994b7b13aa96d

* Obsolete test clean up (Tao Liu)
* Remove the old flow (Tao Liu)
* minor fix, update README for A extension support (Tao Liu)
* Add basic atomic instruction test (Tao Liu)
* Add RV32A/RV64A instructions (google/riscv-dv#95) (Tao Liu)
* Fix the missing GPR save operations for exception handling (Tao Liu)
* Generate handshake sequence to communicate with testbench (Udi)
* Fix compare error (Tao Liu)
* Fix compare error (Tao Liu)
* Initial signature enum for handshake protocol (Udi)
2019-08-26 11:41:37 -07:00
taoliug
e2b9c17c0b
Update google_riscv-dv to e81acc9 (#257)
Update code from upstream repository https://github.com/google/riscv-
dv to revision e81acc9ab4f692ff205a207c2dc3d9f2b0284d39

* Merge pull request #89 from google/dev (taoliug)
* Fix mtvec alignement (Tao Liu)
2019-08-21 18:22:58 -07:00
taoliug
a752277247
Update google_riscv-dv to 73274f2 (#254)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 73274f227000f1316cb201a8503aad437e427948

* Merge pull request #88 from google/dev (taoliug)
* Fix spike log processing issue (Tao Liu)
* Merge pull request #87 from google/dev (udinator)
* Add vectored interrupt support (Tao Liu)
* Merge pull request #85 from udinator/debug (udinator)
* Add debug sub-programs, and extra options to generator (Udi)
* Merge pull request #84 from imphil/fix-apache-urls (taoliug)
* Fix license URLs in comments (Philipp Wagner)
2019-08-21 17:14:15 -07:00
udinator
6ccd2b698d Update google_riscv-dv to google/riscv-dv@7cce16c (#246)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 7cce16c0a212c8713a82516fbf8f2570d3dc4505

* Update spike log processing script to include full trace information
  (Tao Liu)
* Add new tests (Tao Liu)
* Add basic debug test functionality (Udi)
* fix spelling error, fix output directory arg (Udi)
* Add shorten option (dang hai)
* Support SAIL-RISCV ISSi, update README (Tao Liu)
* Fix CSR map copy issue (Tao Liu)
2019-08-16 09:43:27 -07:00
taoliug
7eecbd1b05
Update google_riscv-dv to 63fa0ca (#241)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 63fa0ca922ecf10f3cd733d15a0a79a7937a591e

* Merge pull request #74 from google/dev (taoliug)
* Add gcc compile options, fix unaligned load/store (Tao Liu)
* Merge pull request #72 from google/dev (taoliug)
* Properly disable branch instruction in push/pop stack operations
  (Tao Liu)
2019-08-14 17:16:44 -07:00
udinator
e087e32490 Update google_riscv-dv to google/riscv-dv@07599f6 (#240)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 07599f689a385794cb73932922008bdbe8131d82

* Fix introduced TypeError in run.py (Udi)
2019-08-13 15:03:12 -07:00
udinator
97105f42b1 Update google_riscv-dv to google/riscv-dv@e905e9f (#234)
Update code from upstream repository https://github.com/google/riscv-
dv to revision e905e9f134e0b7cf7da491218d1a30c75ce8649a

* add pass_val and fail_val into csr test flow for EOT correctness
  checking (Udi)
* Support unaligned load/store (Tao Liu)
* refactored test generation logic (Udi)
* refactored test generation logic (Udi)
* Give error when mutually exclusive between -co, and -so argument
  (dang hai)
* documentation, and small fixes (Udi)
* no_iss bug (Udi)
* no_iss/no_post_compare optional, CSR read_only is now only specified
  at field level granularity (Udi)
* made no_iss optional (Udi)
* rm print (Udi)
* setup_logging call (Udi)
* undo overriding --verbose in run.py, comment cleanup in csr gen
  script (Udi)
* missed verbose arguments (Udi)
* verbose arg (Udi)
* updated csr description, integrated csr test into flow (Udi)
* updated csr description, integrated csr test into flow (Udi)
* Enhance verbose information by logging instead of using print (dang
  hai)
* Report date time for output directory (dang hai)
* Add main entry point for run.py (dang hai)
* Separate command line parser by function (dang hai)
* Skip generating S/U mode program for machine mode test (Tao Liu)
* minor update to README.md (Tao Liu)
* Update the README.md to match command reference from --help (Tao
  Liu)
* Ignore untrack file from python script (dang hai)
* Make questa work for new YAML based regression flow (dang hai)
* Fix typo in README (Tao Liu)
* Fix README google/riscv-dv#54 (Tao Liu)
* changed formatting of generator option table (Udi)
2019-08-12 16:22:07 -07:00
taoliug
ba5c63b8d1 Update google_riscv-dv to a07e0a7 (#203)
Update code from upstream repository https://github.com/google/riscv-
dv to revision a07e0a726edf0230314c08d31546eecbed23054b

* Merge pull request #53 from google/flow (taoliug)
* Update README file for the new flow (Tao Liu)
* Merge pull request #52 from google/flow (taoliug)
* Add timeout mechanism to the flow (Tao Liu)
* Merge pull request #51 from google/flow (taoliug)
* Simulation flow update (Tao Liu)
* Merge pull request #50 from udinator/master (taoliug)
* added license for csr_template.yaml (Udi)
* Merge pull request #49 from google/dev (taoliug)
* Update log process script (Tao Liu)
* Merge pull request #48 from google/dev (taoliug)
* Fix illegal instruction issue (Tao Liu)
* Merge pull request #47 from google/dev (taoliug)
* Refactor the simulation flow (Tao Liu)
* Merge pull request #45 from danghai/master (taoliug)
* Add .gitignore to remove untracked files (danghai)
* Fix warning from Questa optmize (danghai)
* Add optimize log file for Questa simulator (danghai)
* New YAML based simulation flow (Tao Liu)
* Merge pull request #40 from scottj97/typos-redone (taoliug)
* Fix typos in comments (Scott Johnson)
* Fix typos/grammar in README (Scott Johnson)
* Merge pull request #43 from udinator/master (taoliug)
* use hex format in YAML description (Udi)
* CSR test description (Udi)
* removed run script (Udi)
* Modified CSR test generation code to adhere to style guidelines.
  (Udi)
* Merge pull request #41 from vandanaprabhu/questa (taoliug)
* CSR Generation Script and YAML template (Udi)
* Prevent Xcelium from attempting to run a simulation during the
  compile step (Scott Johnson)
* Document support for Questa (Scott Johnson)
* Fix simulation-time warnings from Mentor Questa (Scott Johnson)
* Fix compile warnings from Mentor Questa (Scott Johnson)
* Fix warning from Questa compiler (Scott Johnson)
* Fix warning from Questa compiler (Scott Johnson)
* Adding support for using the Questa simulator (Vandana Prabhu)
* Pass proper seed to Cadence Xcelium simulator (Scott Johnson)
* Convert compile commands to functions instead of variables (Scott
  Johnson)
2019-08-01 09:53:26 -07:00
taoliug
53ce0142e2
Update google_riscv-dv to 112dcc2 (#180)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 112dcc2e669f124dfe48c35a09477603c3ccb180

* Merge pull request #39 from google/dev (taoliug)
* CSR instruction update (Tao Liu)
2019-07-23 07:10:45 -07:00
taoliug
74e841b0cd
Update google_riscv-dv to 4e0d063 (#178)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 4e0d063fea574cfae55c5bb627771b69d9899899

* Merge pull request #38 from google/dev (taoliug)
* Fix illegal instruction test issue Fix Xcelium compile failure #37
  (Tao Liu)
2019-07-19 16:15:12 -07:00
taoliug
6b49f32019
Update google_riscv-dv to 2e5a401 (#159)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 2e5a40145a367ac3b04f78fee02c5011022719fd

* Merge pull request #36 from google/dev (taoliug)
* Add basic debug mode support (Tao Liu)
2019-07-15 15:44:16 -07:00
taoliug
1d75e4c8b9
Update google_riscv-dv to 084fa3a (#152)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 084fa3a4debb682b34c9b7f9b17342bb06619a3b

* Merge pull request #35 from google/dev (taoliug)
* Add timeout mechanism for the regression script (Tao Liu)
* Merge pull request #34 from google/dev (taoliug)
* Add check for the toolchain path setup (Tao Liu)
2019-07-12 11:06:46 -07:00
taoliug
ec89314a20
Update google_riscv-dv to 949552f (#127)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 949552f964eec9d058c7c90889bdd5b80d1e60ad

* Merge pull request #33 from google/dev (taoliug)
* Add control for the privileged CSR checking (Tao Liu)
* Merge pull request #32 from google/dev (taoliug)
* Fix minor issue in comparing script (Tao Liu)
2019-07-09 13:13:30 -07:00
taoliug
2d66834f14
Integrate riscv-dv upstream changes (#107)
* Remove all local patches

* Update google_riscv-dv to 00739df

Update code from upstream repository https://github.com/google/riscv-
dv to revision 00739df0ec744986934097bebcde3ebf5a4fdf81

* Merge pull request #30 from google/dev (taoliug)
* Fix LSF options (Tao Liu)
* Refactoring to make extension easier (Tao Liu)
* Merge pull request #29 from google/dev (taoliug)
* Add a sample program (Tao Liu)
* Merge pull request #28 from google/dev (taoliug)
* Move riscv_core_setting to a separate folder (Tao Liu)
* Merge pull request #27 from google/dev (taoliug)
* Add ebreak/wfi test, more regression control (Tao Liu)
* Merge pull request #26 from google/dev (taoliug)
* Add support for GPR based comparison (Tao Liu)

* Add ibex extensions for riscv_dv
2019-07-01 08:59:31 -07:00
taoliug
d77bc49595
Import riscv-dv @b4bd0c6cff0456111be966a11c1bd0aeec2d96e4 (#69)
* update ibex patch file

* Update google_riscv-dv to b4bd0c6

Update code from upstream repository https://github.com/google/riscv-
dv to revision b4bd0c6cff0456111be966a11c1bd0aeec2d96e4

* Merge pull request #24 from google/dev (taoliug)
* Add option to skip reading scratch register (Tao Liu)
2019-06-06 17:27:20 -07:00
taoliug
7ec87d8044
Update google_riscv-dv to be14080 (#57)
Update code from upstream repository https://github.com/google/riscv-
dv to revision be14080425cc3b9a5b33c6c29962893c890c62ee

* Merge pull request #23 from google/dev (taoliug)
* Add privileged CSR implementation configuration (Tao Liu)
2019-06-03 15:05:35 -07:00
Tao Liu
bdb089d456 Update google_riscv-dv to 215e064
Update code from upstream repository https://github.com/google/riscv-
dv to revision 215e0646ae9909aa0e78d6e91f4f33ed77f95e43
2019-05-31 17:39:28 +01:00
taoliug
cd15ce88be Add riscv-dv vendor in script and patches (#52)
Add riscv-dv vendor configuration and patches as basis for including the RISC-V DV code in a follow-up commit.
2019-05-31 08:58:21 +01:00