The RISC-V Debug Specification (current release 1.0.0-rc4) in Section
A.2 states that the PMP must not disallow accesses to addresses of the
Debug Module when the hart is in debug mode, regardless of how the PMP
is configured. This commit changes the PMP accordingly.
Signed-off-by: Andreas Kurth <adk@lowrisc.org>
This sets the C++ standard that's being used for a compiler that's
building a Verilator simulation. Recent versions of Verilator (since
5.020) require the compiler to be in C++14 mode, so passing -std=c++11
breaks the build with them.
Looking at history, -std=c++14 has been supported since GCC
6.1 (released in 2016), so I don't think this argument is going to
cause any tooling problems.
The ibex_top_tracing module takes a ram_cfg_i for something to pass
through to the RAM. Use the named zero (RAM_1P_CFG_DEFAULT) instead of
building it by hand: now we get the right width.
This commit protects the core_busy_o signal using a multi-bit encoding
to reduce the chances of an adversary for glitching this signal to low,
thereby putting the core to sleep and e.g. not handling an alert.
Without this commit, the glitch would only be detected once both the
main core and the shadow core wake up again and the comparison of the
core_busy_o signals continues.
This resolveslowRISC/Ibex#1827.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This allows us to model stuff more closely. This depends on Spike
version ibex-cosim-v0.2 (which is rebased onto a master branch commit
supporting these more specific ISA strings).
Updated the parameters with respect to top_earlgrey.hjson in OpenTitan
repository. For other builds, kept the previously undeclared parameters
as their default values.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This is necessary for having VCS support with simple system example.
Because in the ibex_simple_system_main.cc we are including some
Verilator exclusive header files.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Previously integrity checks for incoming memory reads and integrity
generation for outgoing memory writes were handled within ibex_lockstep
and weren't duplicated.
This moves the integrity checks and generation into the core so they are
replicated and checked as part of the lockstep mechanism.
Additionally it generates a bus error on any memory integrity check
failure. This will result in Ibex taking an exception if any data read
or instruction fetch has bad integrity.
This is to allow more consistent signalling in systems that integrate
Ibex (e.g. OpenTitan) so bus integrity errors external to Ibex and one's
detected within Ibex can be fed into the same alert whilst seperating
out Ibex's various internal alert causes.
This commit includes switching to a scrambling RAM primitive for
ICache data and tag RAMs. Also introduces minor changes to ICache
to handle scrambling key valid signal.
It also includes a minor bug fix regarding not initializing
`fill_way_q` signal without ResetAll parameter. When the parameter
is not set and we have our first hit right after ICache enables,
the signal hangs.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.
Ibex testbench extended to generate the expected bits.
All other top-levels modified to add the new signals (which are mostly
ignored).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.
There are no functional changes in this commit, only wiring.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
f29a0f7a7115e03fba734b1c00691c253aceb07e. The list of OpenTitan
changes that are merged in appears at the bottom of the commit.
There are some manual changes needed to adapt the code to work with
these changes.
- The ICache monitors need some extra types to adapt to the (rather
odd) data model that the OpenTitan dv_lib code now uses, where a
monitor needs to know an agent's associated sequence type.
- Verilator simulations now use MemArea slightly differently
OpenTitan changes:
* [dv] Allow monitor items to have different types from sequence items
(Rupert Swarbrick)
* [dvsim] Fix primary_cfg handling (Srikrishna Iyer)
* [dvsim] Deal with non unicode chars in log files (Srikrishna Iyer)
* [dvsim] Added common build fail patterns (Srikrishna Iyer)
* [dvsim] Minot cleanup to the lint flow (Srikrishna Iyer)
* [dvsim] Minor cleanups to to formal flow (Srikrishna Iyer)
* [dvsim] Fixes to UNR and cov analysis flows (Srikrishna Iyer)
* [dvsim] Very minor cleanup of Deploy class (Srikrishna Iyer)
* [dvsim] LsfLauncher report early errors as F (Srikrishna Iyer)
* [dvsim] Minor fix in clean_odirs function (Srikrishna Iyer)
* [chip dv] Set +sw_images as comma-separated list (Srikrishna Iyer)
* [flash_ctrl] Split tl intefaces for flash_ctrl and prim_flash_cfg
(Timothy Chen)
* [keymgr] Fix input value checks (Timothy Chen)
* [formal/script] Update generic formal flow naming from `fpv` to
`formal` (Cindy Chen)
* [top, prim] Address wmask and data width mismatch issue (Timothy
Chen)
* [dvsim] Add GUI mode for running simulations (Srikrishna Iyer)
* [dv] Fix reg backdoor (Weicai Yang)
* [dpi] Make an "ECC32" flavour of MemArea (Rupert Swarbrick)
* [uvmdvgen] Fix has_interrupts in env_cfg (Cindy Chen)
* [dvsim] Keep dependencies list (Srikrishna Iyer)
* [prim_prince] Reverse the k0||k1 mapping to match with the paper
(Michael Schaffner)
* [dvsim] Fix printing of last 10 lines (Srikrishna Iyer)
* [primgen] Minor fix to enable types with underscores (Michael
Schaffner)
* [dvsim] Prevent command echo suppression (Srikrishna Iyer)
* [dvsim] Spot fixes for LSF and internal launcher (Srikrishna Iyer)
* [sva] csr assertion dependency update (Cindy Chen)
* [memutil] Change DpiMemUtil so that it no longer owns MemAreas
(Rupert Swarbrick)
* [memutil] Factor out MemArea as a class (Rupert Swarbrick)
* [prim] Split out PRESENT and PRINCE support from prim:all (Rupert
Swarbrick)
* [fpv/otp_ctrl] Disable assertions due to lc_esc_en (Cindy Chen)
* [prim_prince] Annotate some arrays to avoid UNOPTFLAT warnings
(Rupert Swarbrick)
* [top] Hook up latest ast ports and complete a few other integration
(Timothy Chen)
* Eliminate `#pragma once` in favor of include guards (Chris Frantz)
* [sw,dv] Update headers to pass fix_include_guards.py (Alex Bradbury)
* [xbar/dv] Fix assertion error due to short reset (Weicai Yang)
* [sram] Add memory initialization (Timothy Chen)
* [uvmdvgen] Update links in checklist template (Philipp Wagner)
* [dv/uvmdvgen] Add comment for testplan (Cindy Chen)
* [dv/top_earlgrey] chip csr_aliasing timeout (Cindy Chen)
* [dvsim] Cosmetic updates to launcher methods (Srikrishna Iyer)
* [dv] Update csr_wr to support field write (Weicai Yang)
* [dv/common] Fix regression warnings (Cindy Chen)
* [dv] Get blocks with multiple device interfaces working with chip DV
(Rupert Swarbrick)
* [doc] Use relative links in Hjson-related shortcodes (Philipp
Wagner)
* [dvsim] minor enhancement to clean_odir (Srikrishna Iyer)
* [dvsim] Statically display jobs' status (Srikrishna Iyer)
* [dvsim] Do weighted scheduling of jobs (Srikrishna Iyer)
* [dvsim] Schedule jobs by dependency (Srikrishna Iyer)
* [dv] Xcelium UNR typo (Srikrishna Iyer)
* [dvsim] Implement LsfLauncher (Srikrishna Iyer)
* [dv/chip] solve same_csr_outstanding_timeout (Cindy Chen)
* [dv] make dv_base_agent work for high-level agent (Weicai Yang)
* [tools/dv] added UNR flow for xcelium (Rasmus Madsen)
* [prim] Split prim:subreg out of prim:all (Rupert Swarbrick)
* [prim] Split prim_alert_* out of prim:all (Rupert Swarbrick)
* [prim] Split out fifos into a prim_fifo core (Rupert Swarbrick)
* [prim] Split out arbiters into a prim_arbiter core (Rupert
Swarbrick)
* [prim] Make prim:flop_2sync depend on prim:flop (Rupert Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
The -Wwarn-IMPERFECTSCH flag is suggested in the Verilator docs (to
help spot if we get a clock gating hint wrong). The waiver is no
longer needed because we now add the relevant hint in the
RTL (vendored in prim_generic_clock_gating.sv from OpenTitan).
Previous lint fix was incorrect. The 'always_comb' block here should be
an 'always'. It is not combinational logic but rather an infinite loop
to generate a clock when running in a simulator that isn't verilator
(e.g. under simple-system under VCS) so the use of 'always' is
appropriate.
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
This commit replaces the previous combination of `RV32M` bit parameter
used to en/disable the M extension and the `MultiplierImplementation`
used to select the multiplier implementation by a single enum parameter.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
* Mention the need to install `libelf-dev`. Thanks to Bert Pieters for
reporting this.
* Guide users to install our Python dependencies, including fusesoc and
edalize, from `python-requirements.txt`, to ensure they have the
right version.
* Prefer ELF files for Verilator simulations. This makes it easier to
use existing ELF files from another software build system.
Fixes#1019
- The "PINCONNECTEMPTY" waiver is part of our normal waiver file, no need
to add it to the tool invocation.
- Recent versions of Verilator choose good defaults for MAKE_OPTS,
passing it explicitly overrides the settings.
- All Verilator code is now lint clean, we can remove `-Wno-fatal`.
- FST traces are not much slower then VCD traces any more in recent
Verilator versions, remove the respective comment.
- Align comment about the compile/sim time for tracing with other files
and OpenTitan.
This commit contains some final optimizations regarding the bit
manipulation extension as well as the parametrization into a balanced
version and a full performance version.
Balanced Version:
* Supports ZBB, ZBS, ZBF and ZBT extensions
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i]
* Everything else completes in a single cycle.
Full Version:
* Supports all 32b sub extensions.
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i], crc32[c], bext, bdep
* Everything else completes in a single cycle.
Notable Changes:
* bext/bdep are now multi-cycle: Sharing additional register
with multiplier module
* grev/gorc instructions are implemented in separate structures
rather than sharing the shifter or butterfly network.
* Speed up decision on using rs1 or rs3 for alu_operand_a by
introducing single-bit register, to identify ternary
instructions in their first cycle.
* Introduce enumerated parameter to chose bit manipulation
implementation
Signed-off-by: ganoam <gnoam@live.com>
