- The RISC-V Debug Spec v.0.13.2 (p.41) mandates that the core
debug CSRs dcsr, dpc, dscratch0 and dscratch1 must not be
accessible if not in debug mode. Fixes#275
- Instantiate generic PMP module
- Wire up I-side and D-side PMP faults
- The output of the PMP check is used to gate external bus requests from the
I-side and LSU
- Each of those units progresses with their request as-if it was granted
externally and registers the PMP error
- The error is then sent to the controller at the appropriate time to trigger
an exception
This commit makes the BASE field of the `mtvec` CSR writable to
allow changing the trap-vector base address at runtime without
changing the boot address input. Similar to the boot address,
the trap-vector base address must always be aligned to 256 bytes.
At bootup, the trap-vector base address is initialized to the boot
address.
This commit resolveslowrisc/ibex#118.
Most of this work has been done by @ivanmgribeiro as part of
lowrisc/ibex#193.
This adds Verilator lint support to our fusesoc core file. A waiver file
is created to waive all well-understood lint warnings. The UNOPTFLAT
warnings are not well understood at the moment, they are waived for now
and further discussion is expected to happen in a GH issue (referenced
in the waiver).
Run with
```
fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core
```
The waiver file support requires edalize >= 0.1.5.
