This commit adds 15 local fast interrupt lines managed through
the `mie` and `mip` CSRs directly, and removes the old legacy
interrupts including the internal controller.
This file doesn't contain defines any more, but a normal SV package.
The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.
Fixeslowrisc/ibex#173
The ibex_tracer_define.sv file was removed from the FuseSoC core files,
but not from the src_files.yml (for Bender) and the .f file.
This is in line with the changes made in
f12b94c2a2.
- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include'
directory, since these files are not actually included.
- Remove ibex_config.sv, it's mostly unused code. The remaining defines,
SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should
be set through command-line flags to the simulation/synthesis tools.
Initial version by Nils Gräf.
This commit switches the ibex core from a custom debug system to an
execution-based, standard RISC-V debug system. The port is based on a
port done for the RI5CY core.
