Commit graph

8 commits

Author SHA1 Message Date
Greg Chadwick
346eacb46c [cosim] Add write suppress support
When Ibex does a load that receives data with bad integrity it
suppresses the write to the destination register. The implements
matching functionality for cosim.
2022-11-07 16:24:48 +00:00
Canberk Topal
715292ce55 [cosim] Cosim integration of internal NMI
This commit is mainly an extension to cosim environment to drive the newly
introduced state variable `nmi_int` in Spike.

This commit
 - Extends RVFI interface by a single bit (ext_nmi_int)
 - Configures cosim to set nmi_int inside Spike

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2022-11-07 16:24:48 +00:00
Greg Chadwick
4084dc4a46 [cosim] Fix spike cosim instruction count
The count wasn't being initialised in the constructor and should be of
type 'unsigned int'.
2022-09-30 09:41:07 +01:00
Greg Chadwick
70186c57ae [rtl] Add ic_scr_key_valid field to CPUCTRL (renamed CPUCTRLSTS)
The ic_scr_key_valid field indicates whether the ICache scrambling key
is valid.

CPUCTRL is also renamed CPUCTRLSTS as it contains both control and
status bits.
2022-09-22 16:17:31 +01:00
Canberk Topal
1e613cc7f4 [cosim,dv] Add support to set mcount registers
Extends RVFI connections further to include 30 mhpmcounterX registers.
Sets them up before every cosim step to let Spike know their real values.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2022-07-25 08:51:31 +01:00
Rupert Swarbrick
36a9abbf1c Use ifndef to avoid re-declaration warnings in *cosim_dpi.svh 2022-02-17 16:19:03 +00:00
Greg Chadwick
b57cad5387 [dv] Add matched instruction count to cosim 2021-11-12 09:39:38 +00:00
Greg Chadwick
648fadb34a [dv] Add co-simulation framework 2021-10-15 11:30:35 +01:00