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64 lines
3 KiB
Markdown
64 lines
3 KiB
Markdown
# Ibex RISC-V Core
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Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements
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the RV32IMC instruction set architecture.
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<p align="center"><img src="doc/images/blockdiagram.svg" width="650"></p>
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Ibex offers several configuration parameters to meet the needs of various application scenarios.
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The options include two different choices for the architecture of the multiplier and divider unit,
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as well as the possibility to drop the support for the "M" extension completely. In addition, the
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"E" extension can be enabled when opting for a minimum-area configuration.
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This core was initially developed as part of the [PULP platform](https://www.pulp-platform.org)
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under the name "Zero-riscy" \[[1](https://doi.org/10.1109/PATMOS.2017.8106976)\], and has been
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contributed to [lowRISC](https://www.lowrisc.org) who maintains it and develops it further. It is
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under active development, with further code cleanups, feature additions, and test and verification
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planned for the future.
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## Documentation
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The Ibex user manual can be
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[read online at ReadTheDocs](https://ibex-core.readthedocs.io/en/latest/). It is also contained in
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the `doc` folder of this repository.
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## Contributing
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We highly appreciate community contributions. To ease our work of reviewing your contributions,
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please:
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* Create your own branch to commit your changes and then open a Pull Request.
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* Split large contributions into smaller commits addressing individual changes or bug fixes. Do not
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mix unrelated changes into the same commit!
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* Write meaningful commit messages. For more information, please check out the [contribution
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guide](https://github.com/lowrisc/ibex/blob/master/CONTRIBUTING.md).
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* If asked to modify your changes, do fixup your commits and rebase your branch to maintain a
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clean history.
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When contributing SystemVerilog source code, please try to be consistent and adhere to [our Verilog
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coding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).
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To get started, please check out the ["Good First Issue"
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list](https://github.com/lowrisc/ibex/issues?q=is%3Aissue+is%3Aopen+label%3A%22Good+First+Issue%22).
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## Issues and Troubleshooting
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If you find any problems or issues with Ibex or the documentation, please check out the [issue
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tracker](https://github.com/lowrisc/ibex/issues) and create a new issue if your problem is
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not yet tracked.
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## Questions?
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Do not hesitate to contact us, e.g., on our public [Ibex channel on
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Zulip](https://lowrisc.zulipchat.com/#narrow/stream/198227-ibex)!
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## License
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Unless otherwise noted, everything in this repository is covered by the Apache
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License, Version 2.0 (see LICENSE for full text).
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## References
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1. [Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of
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ultra-low-power RISC-V cores for Internet-of-Things applications."
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_27th International Symposium on Power and Timing Modeling, Optimization and Simulation
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(PATMOS 2017)_](https://doi.org/10.1109/PATMOS.2017.8106976)
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