mirror of
https://github.com/lowRISC/ibex.git
synced 2025-04-20 11:57:12 -04:00
44b033cf8b
- Add required signals to top-level - Propagate error through fetch stages - Add new exception type - Update documentation for new exception type - Resolves issue #109
115 lines
6 KiB
ReStructuredText
115 lines
6 KiB
ReStructuredText
.. _core-integration:
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Core Integration
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================
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The main module is named ``ibex_core`` and can be found in ``ibex_core.sv``.
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Below, the instantiation template is given and the parameters and interfaces are described.
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Instantiation Template
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----------------------
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.. code-block:: verilog
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ibex_core #(
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.MHPMCounterNum (0),
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.MHPMCounterWidth (40),
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.RV32E (0),
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.RV32M (1),
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.DmHaltAddr (32'h1A110800),
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.DmExceptionAddr (32'h1A110808)
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) u_core (
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// Clock and reset
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.clk_i (),
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.rst_ni (),
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.test_en_i (),
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// Configuration
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.core_id_i (),
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.cluster_id_i (),
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.boot_addr_i (),
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// Instruction memory interface
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.instr_req_o (),
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.instr_gnt_i (),
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.instr_rvalid_i (),
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.instr_addr_o (),
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.instr_rdata_i (),
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.instr_err_i (),
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// Data memory interface
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.data_req_o (),
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.data_gnt_i (),
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.data_rvalid_i (),
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.data_we_o (),
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.data_be_o (),
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.data_addr_o (),
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.data_wdata_o (),
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.data_rdata_i (),
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.data_err_i (),
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// Interrupt inputs
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.irq_software_i (),
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.irq_timer_i (),
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.irq_external_i (),
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.irq_fast_i (),
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.irq_nm_i (),
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// Debug interface
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.debug_req_i (),
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// Special control signal
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.fetch_enable_i ()
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);
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Parameters
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----------
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| Name | Type/Range | Default | Description |
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+=======================+=============+============+=================================================================+
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| ``MHPMCounterNum`` | int (0..8) | 0 | Number of performance monitor event counters |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``MHPMCounterWidth`` | int (64..1) | 40 | Bit width of performance monitor event counters |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32E`` | bit | 0 | RV32E mode enable (16 integer registers only) |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32M`` | bit | 1 | M(ultiply) extension enable |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``DmHaltAddr`` | int | 0x1A110800 | Address to jump to when entering debug mode |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``DmExceptionAddr`` | int | 0x1A110808 | Address to jump to when an exception occurs while in debug mode |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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Interfaces
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----------
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+-------------------------+-------------------------+-----+----------------------------------------+
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| Signal(s) | Width | Dir | Description |
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+=========================+=========================+=====+========================================+
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| ``clk_i`` | 1 | in | Clock signal |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``rst_ni`` | 1 | in | Active-low asynchronous reset |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``test_en_i`` | 1 | in | Test input, enables clock |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``core_id_i`` | 4 | in | Core ID, usually static, can be read |
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| | | | from :ref:`csr-mhartid` CSR |
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+-------------------------+-------------------------+-----+ +
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| ``cluster_id_i`` | 6 | in | |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``boot_addr_i`` | 32 | in | First program counter after reset |
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| | | | = ``boot_addr_i`` + 0x80, |
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| | | | see :ref:`exceptions-interrupts` |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``instr_*`` | Instruction fetch interface, see :ref:`instruction-fetch` |
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+-------------------------+------------------------------------------------------------------------+
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| ``data_*`` | Load-store unit interface, see :ref:`load-store-unit` |
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+-------------------------+------------------------------------------------------------------------+
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| ``irq_*`` | Interrupt inputs, see :ref:`exceptions-interrupts` |
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+-------------------------+------------------------------------------------------------------------+
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| ``debug_*`` | Debug interface, see :ref:`debug-support` |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``fetch_enable_i`` | 1 | in | Enable the core, won't fetch when 0 |
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+-------------------------+-------------------------+-----+----------------------------------------+
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