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124 lines
8.8 KiB
ReStructuredText
124 lines
8.8 KiB
ReStructuredText
.. _performance-counters:
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Performance Counters
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====================
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Ibex implements performance counters according to the RISC-V Privileged Specification, version 1.11 (see Hardware Performance Monitor, Section 3.1.11).
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The performance counters are placed inside the Control and Status Registers (CSRs) and can be accessed with the ``CSRRW(I)`` and ``CSRRS/C(I)`` instructions.
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Ibex implements the clock cycle counter ``mcycle(h)``, the retired instruction counter ``minstret(h)``, as well as the 29 event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)`` and the corresponding event selector CSRs ``mhpmevent3`` - ``mhpmevent31``, and the ``mcountinhibit`` CSR to individually enable/disable the counters.
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``mcycle(h)`` and ``minstret(h)`` are always available and 64 bit wide.
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The ``mhpmcounter`` performance counters are optional (unavailable by default) and parametrizable in width.
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Event Selector
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--------------
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The following events can be monitored using the performance counters of Ibex.
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+--------------+------------------+---------------------------------------------------------+
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| Event ID/Bit | Event Name | Event Description |
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+==============+==================+=========================================================+
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| 0 | NumCycles | Number of cycles |
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+--------------+------------------+---------------------------------------------------------+
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| 2 | NumInstrRet | Number of instructions retired |
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+--------------+------------------+---------------------------------------------------------+
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| 3 | NumCyclesLSU | Number of cycles waiting for data memory |
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+--------------+------------------+---------------------------------------------------------+
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| 4 | NumCyclesIF | Cycles waiting for instruction fetches, i.e., number of |
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| | | instructions wasted due to non-ideal caching |
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+--------------+------------------+---------------------------------------------------------+
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| 5 | NumLoads | Number of data memory loads. Misaligned accesses are |
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| | | counted as two accesses |
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+--------------+------------------+---------------------------------------------------------+
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| 6 | NumStores | Number of data memory stores. Misaligned accesses are |
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| | | counted as two accesses |
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+--------------+------------------+---------------------------------------------------------+
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| 7 | NumJumps | Number of unconditional jumps (j, jal, jr, jalr) |
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+--------------+------------------+---------------------------------------------------------+
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| 8 | NumBranches | Number of branches (conditional) |
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+--------------+------------------+---------------------------------------------------------+
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| 9 | NumBranchesTaken | Number of taken branches (conditional) |
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+--------------+------------------+---------------------------------------------------------+
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| 10 | NumInstrRetC | Number of compressed instructions retired |
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+--------------+------------------+---------------------------------------------------------+
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The event selector CSRs ``mhpmevent3`` - ``mhpmevent31`` define which of these events are counted by the event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)``.
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If a specific bit in an event selector CSR is set to 1, this means that events with this ID are being counted by the counter associated with that selector CSR.
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If an event selector CSR is 0, this means that the corresponding counter is not counting any event.
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Controlling the counters from software
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--------------------------------------
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By default, all available counters are enabled after reset.
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They can be individually enabled/disabled by overwriting the corresponding bit in the ``mcountinhibit`` CSR at address ``0x320`` as described in the RISC-V Privileged Specification, version 1.11 (see Machine Counter-Inhibit CSR, Section 3.1.13).
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In particular, to enable/disable ``mcycle(h)``, bit 0 must be written. For ``minstret(h)``, it is bit 2. For event counter ``mhpmcounterX(h)``, it is bit X.
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The lower 32 bits of all counters can be accessed through the base register, whereas the upper 32 bits are accessed through the ``h``-register.
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Reads to all these registers are non-destructive.
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Parametrization at synthesis time
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---------------------------------
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The ``mcycle(h)`` and ``minstret(h)`` counters are always available and 64 bit wide.
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The event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)`` are parametrizable.
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Their width can be parametrized between 1 and 64 bit through the ``WidthMHPMCounters`` parameter, which defaults to 40 bit wide counters.
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The number of available event counters ``mhpmcounterX(h)`` can be controlled via the ``NumMHPMCounters`` parameter.
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By default (``NumMHPMCounters`` set to 0), no counters are available to software.
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Set ``NumMHPMCounters`` to a value between 1 and 8 to make the counters ``mhpmcounter3(h)`` - ``mhpmcounter10(h)`` available as listed below.
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Setting ``NumMHPMCounters`` to values larger than 8 does not result in any more performance counters.
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Unavailable counters always read 0.
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The association of events with the ``mphmcounter``s is hardwired as listed in the following table.
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+----------------------+----------------+--------------+------------------+
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| Event Counter | CSR Address | Event ID/Bit | Event Name |
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+======================+================+==============+==================+
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| ``mcycle(h)`` | 0xB00 (0xB80) | 0 | NumCycles |
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+----------------------+----------------+--------------+------------------+
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| ``minstret(h)`` | 0xB02 (0xB82) | 2 | NumInstrRet |
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+----------------------+----------------+--------------+------------------+
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| ``mhpmcounter3(h)`` | 0xB03 (0xB83) | 3 | NumCyclesLSU |
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+----------------------+----------------+--------------+------------------+
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| ``mhpmcounter4(h)`` | 0xB04 (0xB84) | 4 | NumCyclesIF |
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| | | | |
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+----------------------+----------------+--------------+------------------+
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| ``mhpmcounter5(h)`` | 0xB05 (0xB85) | 5 | NumLoads |
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| | | | |
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+----------------------+----------------+--------------+------------------+
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| ``mhpmcounter6(h)`` | 0xB06 (0xB86) | 6 | NumStores |
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| | | | |
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+----------------------+----------------+--------------+------------------+
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| ``mhpmcounter7(h)`` | 0xB07 (0xB87) | 7 | NumJumps |
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+----------------------+----------------+--------------+------------------+
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| ``mhpmcounter8(h)`` | 0xB08 (0xB88) | 8 | NumBranches |
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+----------------------+----------------+--------------+------------------+
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| ``mhpmcounter9(h)`` | 0xB09 (0xB89) | 9 | NumBranchesTaken |
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+----------------------+----------------+--------------+------------------+
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| ``mhpmcounter10(h)`` | 0xB0A (0xB8A) | 10 | NumInstrRetC |
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+----------------------+----------------+--------------+------------------+
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Similarly, the event selector CSRs are hardwired as follows.
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The remaining event selector CSRs are tied to 0, i.e., no events are counted by the corresponding counters.
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+----------------------+-------------+-------------+--------------+
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| Event Selector | CSR Address | Reset Value | Event ID/Bit |
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+======================+=============+=============+==============+
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| ``mhpmevent3(h)`` | 0x323 | 0x0000_0008 | 3 |
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+----------------------+-------------+-------------+--------------+
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| ``mhpmevent4(h)`` | 0x324 | 0x0000_0010 | 4 |
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+----------------------+-------------+-------------+--------------+
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| ``mhpmevent5(h)`` | 0x325 | 0x0000_0020 | 5 |
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+----------------------+-------------+-------------+--------------+
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| ``mhpmevent6(h)`` | 0x326 | 0x0000_0040 | 6 |
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+----------------------+-------------+-------------+--------------+
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| ``mhpmevent7(h)`` | 0x327 | 0x0000_0080 | 7 |
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+----------------------+-------------+-------------+--------------+
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| ``mhpmevent8(h)`` | 0x328 | 0x0000_0100 | 8 |
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+----------------------+-------------+-------------+--------------+
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| ``mhpmevent9(h)`` | 0x329 | 0x0000_0200 | 9 |
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+----------------------+-------------+-------------+--------------+
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| ``mhpmevent10(h)`` | 0x32A | 0x0000_0400 | 10 |
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+----------------------+-------------+-------------+--------------+
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