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https://github.com/lowRISC/ibex.git
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24a9c64bf1
This adds a Verilator simulation of Ibex for use in RISC-V Compliance Testing. In addition to ibex itself, the simulation contains a RAM and a memory-mapped helper module for the test software to interact with the outside world. The test framework uses this to dump a "test signature", which is written to a certain part of the memory, and to end the simulation. (In the future, this could be extended to include printf() like functionality.)
120 lines
4.2 KiB
Systemverilog
120 lines
4.2 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Simplistic Ibex bus implementation
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*
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* This module is designed for demo and simulation purposes, do not use it in
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* a real-world system.
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*
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* This implementation doesn't handle the full bus protocol, but makes the
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* following simplifying assumptions.
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*
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* - All devices (slaves) must respond in the next cycle after the request.
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* - Host (master) arbitration is strictly priority based.
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*/
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module bus #(
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parameter NrDevices,
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parameter NrHosts,
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parameter DataWidth = 32,
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parameter AddressWidth = 32
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) (
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input clk_i,
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input rst_ni,
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// Hosts (masters)
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input host_req_i [NrHosts],
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output logic host_gnt_o [NrHosts],
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input [AddressWidth-1:0] host_addr_i [NrHosts],
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input host_we_i [NrHosts],
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input [ DataWidth/8-1:0] host_be_i [NrHosts],
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input [ DataWidth-1:0] host_wdata_i [NrHosts],
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output logic host_rvalid_o [NrHosts],
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output logic [ DataWidth-1:0] host_rdata_o [NrHosts],
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output logic host_err_o [NrHosts],
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// Devices (slaves)
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output logic device_req_o [NrDevices],
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output logic [AddressWidth-1:0] device_addr_o [NrDevices],
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output logic device_we_o [NrDevices],
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output logic [ DataWidth/8-1:0] device_be_o [NrDevices],
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output logic [ DataWidth-1:0] device_wdata_o [NrDevices],
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input device_rvalid_i [NrDevices],
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input [ DataWidth-1:0] device_rdata_i [NrDevices],
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input device_err_i [NrDevices],
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// Device address map
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input [AddressWidth-1:0] cfg_device_addr_base [NrDevices],
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input [AddressWidth-1:0] cfg_device_addr_mask [NrDevices]
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);
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logic [$clog2(NrHosts)-1:0] host_sel_req, host_sel_resp;
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logic [$clog2(NrDevices)-1:0] device_sel_req, device_sel_resp;
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// Master select prio arbiter
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always_comb begin
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for (integer host = NrHosts - 1; host >= 0; host = host - 1) begin
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if (host_req_i[host]) begin
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host_sel_req = $clog2(NrHosts)'(host);
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end
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end
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end
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// Device select
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always_comb begin
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for (integer device = 0; device < NrDevices; device = device + 1) begin
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if ((host_addr_i[host_sel_req] & cfg_device_addr_mask[device])
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== cfg_device_addr_base[device]) begin
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device_sel_req = $clog2(NrDevices)'(device);
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end
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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host_sel_resp <= '0;
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device_sel_resp <= '0;
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end else begin
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// Responses are always expected 1 cycle after the request
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device_sel_resp <= device_sel_req;
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host_sel_resp <= host_sel_req;
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end
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end
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always_comb begin
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for (integer device = 0; device < NrDevices; device = device + 1) begin
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if ($clog2(NrDevices)'(device) == device_sel_req) begin
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device_req_o[device] = host_req_i[host_sel_req];
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device_we_o[device] = host_we_i[host_sel_req];
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device_addr_o[device] = host_addr_i[host_sel_req];
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device_wdata_o[device] = host_wdata_i[host_sel_req];
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device_be_o[device] = host_be_i[host_sel_req];
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end else begin
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device_req_o[device] = 1'b0;
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device_we_o[device] = 1'b0;
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device_addr_o[device] = 'b0;
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device_wdata_o[device] = 'b0;
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device_be_o[device] = 'b0;
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end
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end
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end
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always_comb begin
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for (integer host = 0; host < NrHosts; host = host + 1) begin
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if ($clog2(NrHosts)'(host) == host_sel_resp) begin
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host_rvalid_o[host] = device_rvalid_i[device_sel_resp];
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host_err_o[host] = device_err_i[device_sel_resp];
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host_rdata_o[host] = device_rdata_i[device_sel_resp];
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end else begin
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host_gnt_o[host] = 1'b0;
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host_rvalid_o[host] = 1'b0;
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host_err_o[host] = 1'b0;
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host_rdata_o[host] = 'b0;
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end
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end
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host_gnt_o[host_sel_req] = host_req_i[host_sel_req];
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end
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endmodule
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