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ibex/dv/riscv_compliance/rtl
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Tom Roberts 44b033cf8b [rtl] Add support for instruction fetch errors 
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
2019-08-09 10:44:37 +01:00
..
bus.sv Add simulation for RISC-V compliance testing 2019-08-05 15:49:15 +01:00
ibex_riscv_compliance.sv [rtl] Add support for instruction fetch errors 2019-08-09 10:44:37 +01:00
prim_clock_gating.sv Add simulation for RISC-V compliance testing 2019-08-05 15:49:15 +01:00
ram_1p.sv Add simulation for RISC-V compliance testing 2019-08-05 15:49:15 +01:00
riscv_testutil.sv Add simulation for RISC-V compliance testing 2019-08-05 15:49:15 +01:00