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https://github.com/lowRISC/ibex.git
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24a9c64bf1
This adds a Verilator simulation of Ibex for use in RISC-V Compliance Testing. In addition to ibex itself, the simulation contains a RAM and a memory-mapped helper module for the test software to interact with the outside world. The test framework uses this to dump a "test signature", which is written to a certain part of the memory, and to end the simulation. (In the future, this could be extended to include printf() like functionality.)
70 lines
1.6 KiB
Systemverilog
70 lines
1.6 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Single-port RAM with 1 cycle read/write delay, 32 bit words
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*/
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module ram_1p #(
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parameter int Depth = 128
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) (
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input clk_i,
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input rst_ni,
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input req_i,
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input we_i,
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input [ 3:0] be_i,
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input [31:0] addr_i,
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input [31:0] wdata_i,
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output logic rvalid_o,
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output logic [31:0] rdata_o
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);
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localparam int Aw = $clog2(Depth);
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logic [31:0] mem [Depth];
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logic [Aw-1:0] addr_idx;
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assign addr_idx = addr_i[Aw-1+2:2];
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logic [31-Aw:0] unused_addr_parts;
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assign unused_addr_parts = {addr_i[31:Aw+2], addr_i[1:0]};
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always @(posedge clk_i) begin
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if (req_i) begin
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if (we_i) begin
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for (int i = 0; i < 4; i = i + 1) begin
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if (be_i[i] == 1'b1) begin
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mem[addr_idx][i*8 +: 8] <= wdata_i[i*8 +: 8];
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end
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end
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end
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rdata_o <= mem[addr_idx];
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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rvalid_o <= '0;
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end else begin
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rvalid_o <= req_i;
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end
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end
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`ifdef VERILATOR
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export "DPI-C" task simutil_verilator_memload;
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task simutil_verilator_memload;
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input string file;
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$readmemh(file, mem);
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endtask
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`endif
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`ifdef SRAM_INIT_FILE
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localparam MEM_FILE = `"`SRAM_INIT_FILE`";
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initial begin
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$display("Initializing SRAM from %s", MEM_FILE);
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$readmemh(MEM_FILE, mem);
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end
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`endif
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endmodule
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