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428d057c4a
This file doesn't contain defines any more, but a normal SV package. The diff is best viewed without whitespace changes, as the reindents cause a lof of diff noise. Fixes lowrisc/ibex#173
74 lines
5 KiB
Systemverilog
74 lines
5 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2017 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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package ibex_tracer_pkg;
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import ibex_pkg::*;
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// instruction masks (for tracer)
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parameter logic [31:0] INSTR_LUI = { 25'b?, {OPCODE_LUI } };
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parameter logic [31:0] INSTR_AUIPC = { 25'b?, {OPCODE_AUIPC} };
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parameter logic [31:0] INSTR_JAL = { 25'b?, {OPCODE_JAL } };
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parameter logic [31:0] INSTR_JALR = { 17'b?, 3'b000, 5'b?, {OPCODE_JALR } };
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// BRANCH
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parameter logic [31:0] INSTR_BEQ = { 17'b?, 3'b000, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BNE = { 17'b?, 3'b001, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BLT = { 17'b?, 3'b100, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BGE = { 17'b?, 3'b101, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BLTU = { 17'b?, 3'b110, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BGEU = { 17'b?, 3'b111, 5'b?, {OPCODE_BRANCH} };
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parameter logic [31:0] INSTR_BALL = { 17'b?, 3'b010, 5'b?, {OPCODE_BRANCH} };
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// OPIMM
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parameter logic [31:0] INSTR_ADDI = { 17'b?, 3'b000, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SLTI = { 17'b?, 3'b010, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SLTIU = { 17'b?, 3'b011, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_XORI = { 17'b?, 3'b100, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_ORI = { 17'b?, 3'b110, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_ANDI = { 17'b?, 3'b111, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SLLI = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SRLI = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
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parameter logic [31:0] INSTR_SRAI = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
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// OP
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parameter logic [31:0] INSTR_ADD = { 7'b0000000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SUB = { 7'b0100000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SLL = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SLT = { 7'b0000000, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SLTU = { 7'b0000000, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_XOR = { 7'b0000000, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SRL = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_SRA = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_OR = { 7'b0000000, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
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// SYSTEM
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parameter logic [31:0] INSTR_CSRRW = { 17'b?, 3'b001, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRS = { 17'b?, 3'b010, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRC = { 17'b?, 3'b011, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRWI = { 17'b?, 3'b101, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_ECALL = { 12'b000000000000, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_EBREAK = { 12'b000000000001, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_MRET = { 12'b001100000010, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_DRET = { 12'b011110110010, 13'b0, {OPCODE_SYSTEM} };
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parameter logic [31:0] INSTR_WFI = { 12'b000100000101, 13'b0, {OPCODE_SYSTEM} };
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// RV32M
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parameter logic [31:0] INSTR_DIV = { 7'b0000001, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_DIVU = { 7'b0000001, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_REM = { 7'b0000001, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_REMU = { 7'b0000001, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_PMUH = { 7'b0000001, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_PMULHSU = { 7'b0000001, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
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parameter logic [31:0] INSTR_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
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// LOAD & STORE
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parameter logic [31:0] INSTR_LOAD = {25'b?, {OPCODE_LOAD } };
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parameter logic [31:0] INSTR_STORE = {25'b?, {OPCODE_STORE} };
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// MISC-MEM
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parameter logic [31:0] INSTR_FENCE = { 17'b?, 3'b000, 5'b?, {OPCODE_MISC_MEM} };
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endpackage
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