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e1a7dcf37f
This commit clarifies why CSR-related pipeline flushes are needed (e.g. when enabling interrupts), only introduces them when doing the critical modifications (write/set bits in `mstatus` and `mie` CSRs for enabling interrupts, reads and clears are uncritical for these CSRs), and makes sure the controller is actually able to start handling interrupts while doing a CSR-related pipeline flush. This resolves lowrisc/ibex#6. |
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| .. | ||
| ibex_alu.sv | ||
| ibex_compressed_decoder.sv | ||
| ibex_controller.sv | ||
| ibex_core.f | ||
| ibex_core.sv | ||
| ibex_core_tracing.sv | ||
| ibex_cs_registers.sv | ||
| ibex_decoder.sv | ||
| ibex_ex_block.sv | ||
| ibex_fetch_fifo.sv | ||
| ibex_id_stage.sv | ||
| ibex_if_stage.sv | ||
| ibex_load_store_unit.sv | ||
| ibex_multdiv_fast.sv | ||
| ibex_multdiv_slow.sv | ||
| ibex_pkg.sv | ||
| ibex_prefetch_buffer.sv | ||
| ibex_register_file_ff.sv | ||
| ibex_register_file_latch.sv | ||
| ibex_tracer.sv | ||
| ibex_tracer_pkg.sv | ||