Exact

Exact Union RegExp

Harry Callahan 8762e0f221 [RISCV-DV] Change push_gpr_to_kernel_stack to prevent off-by-one store ... If the DUT comes out of reset and immediately jumps into debug mode, the first routine executed is to push the gpr's to the kernel stack. The register used as the effective stack-pointer is initialized to zero, and the routine reserves the address space (XLEN/4) * 31 to push the GPR's (excluding x0). This routine however assumes that the original value in the sp register is valid to be stored to. This is often not the case out of reset, when it is 0x00000000. Therefore an address range from 0xffffff80 up to and including 0x00000000 (wrapping) is stored to. This patch reserves 32 words instead, preventing the final gpr from writing to an invalid addr in this case. Signed-off-by: Harry Callahan <hcallahan@lowrisc.org> [RISCV-DV] Functional changes to fix nested_interrupt_test		2022-10-28 13:53:40 +01:00
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eembc_coremark	Update eembc_coremark to eembc/coremark@0c91314	2020-03-09 14:41:40 +00:00
google_riscv-dv	[RISCV-DV] Change push_gpr_to_kernel_stack to prevent off-by-one store	2022-10-28 13:53:40 +01:00
lowrisc_ip	Update lowrisc_ip to lowRISC/opentitan@d1be61ba8	2022-08-24 14:42:02 -07:00
patches	[vendor] Update patch file based on upstream OpenTitan	2022-08-05 18:00:25 +01:00
eembc_coremark.lock.hjson	Update eembc_coremark to eembc/coremark@0c91314	2020-03-09 14:41:40 +00:00
google_riscv-dv.lock.hjson	Update google_riscv-dv to google/riscv-dv@ada58fc	2022-10-25 16:07:33 +01:00
google_riscv-dv.vendor.hjson	[dv] Add RISCV-DV patch to fix csr_test	2021-02-04 08:37:00 +00:00
lowrisc_ip.lock.hjson	Update lowrisc_ip to lowRISC/opentitan@d1be61ba8	2022-08-24 14:42:02 -07:00
lowrisc_ip.vendor.hjson	Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd	2022-03-17 18:06:56 +00:00