github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-23 21:39:13 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
ibex/vendor/google_riscv-dv
History
Exact
Harry Callahan 8762e0f221 [RISCV-DV] Change push_gpr_to_kernel_stack to prevent off-by-one store 
If the DUT comes out of reset and immediately jumps into debug mode, the first
routine executed is to push the gpr's to the kernel stack. The register used as
the effective stack-pointer is initialized to zero, and the routine reserves the
address space (XLEN/4) * 31 to push the GPR's (excluding x0).

This routine however assumes that the original value in the sp register is valid
to be stored to. This is often not the case out of reset, when it is 0x00000000.
Therefore an address range from 0xffffff80 up to and including
0x00000000 (wrapping) is stored to.

This patch reserves 32 words instead, preventing the final gpr from writing to
an invalid addr in this case.

Signed-off-by: Harry Callahan <hcallahan@lowrisc.org>

[RISCV-DV] Functional changes to fix nested_interrupt_test
2022-10-28 13:53:40 +01:00
..
.github/workflows Update google_riscv-dv to google/riscv-dv@59dcd8c 2021-04-06 14:13:39 +01:00
docs Update google_riscv-dv to google/riscv-dv@0b62525 2021-02-04 08:37:00 +00:00
euvm Update google_riscv-dv to google/riscv-dv@68e3bca 2022-08-22 09:55:31 +01:00
pygen Update google_riscv-dv to google/riscv-dv@808fb16 2022-08-03 15:06:03 +01:00
scripts Update google_riscv-dv to google/riscv-dv@68e3bca 2022-08-22 09:55:31 +01:00
src [RISCV-DV] Change push_gpr_to_kernel_stack to prevent off-by-one store 2022-10-28 13:53:40 +01:00
target Update google_riscv-dv to google/riscv-dv@0b2b3d6 2022-06-09 09:00:42 +02:00
test Update google_riscv-dv to google/riscv-dv@68e3bca 2022-08-22 09:55:31 +01:00
user_extension Update google_riscv-dv to google/riscv-dv@6cf6b4f 2020-06-18 11:05:30 -07:00
verilog_style Update google_riscv-dv to google/riscv-dv@e6a63ff 2020-05-19 09:40:26 +01:00
yaml Update google_riscv-dv to google/riscv-dv@808fb16 2022-08-03 15:06:03 +01:00
.flake8 Update google_riscv-dv to google/riscv-dv@6cf6b4f 2020-06-18 11:05:30 -07:00
.gitignore Update google_riscv-dv to google/riscv-dv@3cf691d 2020-07-24 00:09:07 -07:00
.metrics.json Update google_riscv-dv to google/riscv-dv@68e3bca 2022-08-22 09:55:31 +01:00
.travis.yml Update google_riscv-dv to google/riscv-dv@6cf6b4f 2020-06-18 11:05:30 -07:00
CONTRIBUTING.md Update google_riscv-dv to 215e064 2019-05-31 17:39:28 +01:00
cov.py Update google_riscv-dv to google/riscv-dv@68e3bca 2022-08-22 09:55:31 +01:00
files.f Update google_riscv-dv to google/riscv-dv@c98d89c (#312) 2019-09-13 14:34:56 -07:00
LICENSE.txt Update google_riscv-dv to 215e064 2019-05-31 17:39:28 +01:00
MANIFEST.in Update google_riscv-dv to google/riscv-dv@42264b7 2020-04-17 17:06:42 -07:00
qrun_option.f Update google_riscv-dv to google/riscv-dv@f7e35d7 (#573) 2020-01-28 15:45:41 -08:00
questa_sim.tcl Update google_riscv-dv to google/riscv-dv@46ec4bc (#417) 2019-10-23 10:46:31 -07:00
README.md Update google_riscv-dv to google/riscv-dv@68e3bca 2022-08-22 09:55:31 +01:00
requirements.txt Update google_riscv-dv to google/riscv-dv@39797b2 2020-10-23 17:00:38 -07:00
riviera_sim.tcl Update google_riscv-dv to google/riscv-dv@42264b7 2020-04-17 17:06:42 -07:00
run.py Update google_riscv-dv to google/riscv-dv@cb4295f 2022-04-01 16:15:35 +02:00
setup.cfg Update google_riscv-dv to google/riscv-dv@d23da38 (#549) 2020-01-09 15:04:39 -08:00
setup.py Update google_riscv-dv to google/riscv-dv@d23da38 (#549) 2020-01-09 15:04:39 -08:00
vcs.compile.option.f Update google_riscv-dv to 215e064 2019-05-31 17:39:28 +01:00

README.md

Overview

RISCV-DV is a SV/UVM based open-source instruction generator for RISC-V processor verification. It currently supports the following features:

  • Supported instruction set: RV32IMAFDC, RV64IMAFDC
  • Supported privileged mode: machine mode, supervisor mode, user mode
  • Page table randomization and exception
  • Privileged CSR setup randomization
  • Privileged CSR test suite
  • Trap/interrupt handling
  • Test suite to stress test MMU
  • Sub-program generation and random program calls
  • Illegal instruction and HINT instruction generation
  • Random forward/backward branch instructions
  • Supports mixing directed instructions with random instruction stream
  • Debug mode support, with fully randomized debug ROM
  • Instruction generation coverage model
  • Handshake communication with testbench
  • Support handcoded assembly test
  • Co-simulation with multiple ISS : spike, riscv-ovpsim, whisper, sail-riscv

Getting Started

Prerequisites

To be able to run the instruction generator, you need to have an RTL simulator which supports SystemVerilog and UVM 1.2. This generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators. Please make sure the EDA tool environment is properly setup before running the generator.

Install RISCV-DV

Getting the source

git clone https://github.com/google/riscv-dv.git

There are two ways that you can run scripts from riscv-dv.

For developers which may work on multiple clones in parallel, using directly run by python3 script is highly recommended. Example:

pip3 install -r requirements.txt    # install dependencies (only once)
python3 run.py --help

For normal users, using the python package is recommended. First, cd to the directory where riscv-dv is cloned and run:

export PATH=$HOME/.local/bin/:$PATH  # add ~/.local/bin to the $PATH (only once)
pip3 install --user -e .

This installs riscv-dv in a mode where any changes within the repo are immediately available simply by running run/cov. There is no need to repeatedly run pip install . after each change. Example for running:

run --help
cov --help

Use below command to install Verible, which is the tool to check Verilog style

verilog_style/build-verible.sh

This is the command to run Verilog style check. It's recommended to run and clean up all the style violations before submit a PR

verilog_style/run.sh

Document

To understand how to setup and customize the generator, please check the full document under docs directory. You can use the makefile to generate the document. HTML preview. You can find the prebuilt document under docs/build/singlehtml/index.html

External contributions and collaborations

RISC-V DV is now contributed to CHIPS Alliance. We have regular meetings to discuss the issues, feature priorities, development progress etc. Please join the mail group for latest status.

Please refer to CONTRIBUTING.md for license related questions.

Supporting model

Please file an issue under this repository for any bug report / integration issue / feature request. We are looking forward to knowing your experience of using this flow and how we can make it better together.

Disclaimer

This is not an officially supported Google product.