github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-20 03:47:15 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
ibex/dv/cosim
History
Exact
Greg Chadwick 1120e8ddbf [dv] Improve interrupt signalling to cosim 
Previously any changes in interrupt state or debug requests were
strictly associated with retired instructions. This causes cosim
mismatches where a lower priority interrupt occurs in time before a
higher priority interrupt or debug request but between instruction
fetches/retirements so both the low and high priority interrupts are
signalled with the instruction retirement.

This introduces a way for the RVFI to signal an interrupt has occurred
that isn't associated with an instruction retirement to allow the cosim
to see the seperation in time between different interrupts and debug
requests and hence model behaviour correctly.
2023-04-27 12:04:22 +00:00
..
cosim.core [dv] Add co-simulation framework 2021-10-15 11:30:35 +01:00
cosim.h [cosim] Add write suppress support 2022-11-07 16:24:48 +00:00
cosim_dpi.cc [cosim] Add write suppress support 2022-11-07 16:24:48 +00:00
cosim_dpi.core [dv] Add co-simulation framework 2021-10-15 11:30:35 +01:00
cosim_dpi.h [cosim] Add write suppress support 2022-11-07 16:24:48 +00:00
cosim_dpi.svh [cosim] Add write suppress support 2022-11-07 16:24:48 +00:00
spike_cosim.cc [dv] Improve interrupt signalling to cosim 2023-04-27 12:04:22 +00:00
spike_cosim.h [dv] Improve interrupt signalling to cosim 2023-04-27 12:04:22 +00:00