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1120e8ddbf
Previously any changes in interrupt state or debug requests were strictly associated with retired instructions. This causes cosim mismatches where a lower priority interrupt occurs in time before a higher priority interrupt or debug request but between instruction fetches/retirements so both the low and high priority interrupts are signalled with the instruction retirement. This introduces a way for the RVFI to signal an interrupt has occurred that isn't associated with an instruction retirement to allow the cosim to see the seperation in time between different interrupts and debug requests and hence model behaviour correctly.
135 lines
4.5 KiB
C++
135 lines
4.5 KiB
C++
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef SPIKE_COSIM_H_
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#define SPIKE_COSIM_H_
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#include <stdint.h>
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#include <deque>
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#include <memory>
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#include <string>
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#include <vector>
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#include "cosim.h"
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#include "riscv/devices.h"
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#include "riscv/log_file.h"
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#include "riscv/processor.h"
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#include "riscv/simif.h"
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#define IBEX_MARCHID 22
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class SpikeCosim : public simif_t, public Cosim {
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private:
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std::unique_ptr<isa_parser_t> isa_parser;
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std::unique_ptr<processor_t> processor;
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std::unique_ptr<log_file_t> log;
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bus_t bus;
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std::vector<std::unique_ptr<mem_t>> mems;
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std::vector<std::string> errors;
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bool nmi_mode;
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typedef struct {
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uint8_t mpp;
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bool mpie;
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uint32_t epc;
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uint32_t cause;
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} mstack_t;
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mstack_t mstack;
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void fixup_csr(int csr_num, uint32_t csr_val);
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struct PendingMemAccess {
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DSideAccessInfo dut_access_info;
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uint32_t be_spike;
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};
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std::vector<PendingMemAccess> pending_dside_accesses;
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bool pending_iside_error;
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uint32_t pending_iside_err_addr;
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typedef enum {
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kCheckMemOk, // Checks passed and access succeded in RTL
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kCheckMemCheckFailed, // Checks failed
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kCheckMemBusError // Checks passed, but access generated bus error in RTL
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} check_mem_result_e;
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check_mem_result_e check_mem_access(bool store, uint32_t addr, size_t len,
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const uint8_t *bytes);
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bool pc_is_mret(uint32_t pc);
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bool pc_is_load(uint32_t pc, uint32_t &rd_out);
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bool pc_is_debug_ebreak(uint32_t pc);
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bool check_debug_ebreak(uint32_t write_reg, uint32_t pc, bool sync_trap);
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bool check_gpr_write(const commit_log_reg_t::value_type ®_change,
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uint32_t write_reg, uint32_t write_reg_data);
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bool check_suppress_reg_write(uint32_t write_reg, uint32_t pc,
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uint32_t &suppressed_write_reg);
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void on_csr_write(const commit_log_reg_t::value_type ®_change);
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void leave_nmi_mode();
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bool change_cpuctrlsts_sync_exc_seen(bool flag);
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void set_cpuctrlsts_double_fault_seen();
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void handle_cpuctrl_exception_entry();
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void initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec,
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uint32_t mhpm_counter_num);
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void early_interrupt_handle();
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unsigned int insn_cnt;
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public:
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SpikeCosim(const std::string &isa_string, uint32_t start_pc,
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uint32_t start_mtvec, const std::string &trace_log_path,
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bool secure_ibex, bool icache_en, uint32_t pmp_num_regions,
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uint32_t pmp_granularity, uint32_t mhpm_counter_num);
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// simif_t implementation
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virtual char *addr_to_mem(reg_t addr) override;
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virtual bool mmio_load(reg_t addr, size_t len, uint8_t *bytes) override;
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virtual bool mmio_store(reg_t addr, size_t len,
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const uint8_t *bytes) override;
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virtual void proc_reset(unsigned id) override;
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virtual const char *get_symbol(uint64_t addr) override;
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// Cosim implementation
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void add_memory(uint32_t base_addr, size_t size) override;
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bool backdoor_write_mem(uint32_t addr, size_t len,
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const uint8_t *data_in) override;
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bool backdoor_read_mem(uint32_t addr, size_t len, uint8_t *data_out) override;
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bool step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
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bool sync_trap, bool suppress_reg_write) override;
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bool check_retired_instr(uint32_t write_reg, uint32_t write_reg_data,
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uint32_t dut_pc, bool suppress_reg_write);
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bool check_sync_trap(uint32_t write_reg, uint32_t pc,
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uint32_t initial_spike_pc);
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void set_mip(uint32_t mip) override;
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void set_nmi(bool nmi) override;
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void set_nmi_int(bool nmi_int) override;
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void set_debug_req(bool debug_req) override;
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void set_mcycle(uint64_t mcycle) override;
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void set_csr(const int csr_num, const uint32_t new_val) override;
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void set_ic_scr_key_valid(bool valid) override;
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void notify_dside_access(const DSideAccessInfo &access_info) override;
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// The spike co-simulator assumes iside and dside accesses within a step are
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// disjoint. If both access the same address within a step memory faults may
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// be incorrectly cause on one rather than the other or the access checking
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// will break.
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// TODO: Work on spike changes to remove this restriction
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void set_iside_error(uint32_t addr) override;
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const std::vector<std::string> &get_errors() override;
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void clear_errors() override;
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unsigned int get_insn_cnt() override;
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};
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#endif // SPIKE_COSIM_H_
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