Exact

Exact Union RegExp

Greg Chadwick 1120e8ddbf [dv] Improve interrupt signalling to cosim ... Previously any changes in interrupt state or debug requests were strictly associated with retired instructions. This causes cosim mismatches where a lower priority interrupt occurs in time before a higher priority interrupt or debug request but between instruction fetches/retirements so both the low and high priority interrupts are signalled with the instruction retirement. This introduces a way for the RVFI to signal an interrupt has occurred that isn't associated with an instruction retirement to allow the cosim to see the seperation in time between different interrupts and debug requests and hence model behaviour correctly.		2023-04-27 12:04:22 +00:00
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core_ibex_csr_if.sv	[ibex/dv] Add clocking blocks to Ibex interfaces	2020-06-22 12:07:40 -07:00
core_ibex_dut_probe_if.sv	[dv] Fix iside error notification to cosim	2022-11-14 16:49:06 +00:00
core_ibex_env.sv	Rework reset handling for UVM env	2022-10-31 17:32:32 +00:00
core_ibex_env_cfg.sv	[dv] Add pass on timeout option	2022-11-17 18:24:41 +00:00
core_ibex_env_pkg.sv	Add a double_fault detector to core_ibex uvm environment	2022-10-17 10:37:04 +01:00
core_ibex_instr_monitor_if.sv	[dv] Add co-simulation environment support to UVM testbench	2021-10-15 11:30:35 +01:00
core_ibex_rvfi_if.sv	[dv] Improve interrupt signalling to cosim	2023-04-27 12:04:22 +00:00
core_ibex_scoreboard.sv	[dv] Double fault detector should sample with clocking block	2023-04-18 16:49:41 +00:00
core_ibex_vseqr.sv	Commenting UVM testbench code, tidy formatting, minor refactoring	2022-07-15 12:45:42 +01:00