ibex/dv/uvm/core_ibex
Pascal Nasahl 8ec0c6f18e [rtl] Harden lockstep enable against FI
Currently, the dual-core lockstep FI mitigation is enabled/disabled
using a single bit.
For transient bit-flips, this is not problematic, as one bit-flip
into this signal and one bit into the Ibex is required to threaten
the security of the system.

However, a permanent stuck-at-0 fault could disable the lockstep
completely by targeting this signal. Then, only a single, additional
fault (transient or permanent) is required.

This PR enhances the FI resilience of the Ibex lockstep by encoding
this single bit into a ibex_mubi_t signal, i.e., a 4-bit multi-bit
signal.

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
2024-01-23 09:14:45 +00:00
..
common [rtl] Fix FI vulnerability in RF 2024-01-04 15:26:32 +00:00
directed_tests [dv,doc] Point reference to lowRISC branch 2023-07-18 08:34:09 +00:00
env [dv] Improve interrupt signalling to cosim 2023-04-27 12:04:22 +00:00
fcov [dv,fcov] Add additional illegal bins to PMP fcov 2023-06-22 11:00:26 +00:00
riscv_dv_extension [dv, fcov] Increase iterations of riscv_mem_intg_error_test 2023-06-22 10:15:49 +00:00
scripts [dv] Fix paths in merge_cov.py 2024-01-11 15:00:52 +00:00
tb [rtl] Harden lockstep enable against FI 2024-01-23 09:14:45 +00:00
tests [rtl] Increase minimum delay for IRQ assertion in new sequence library 2023-04-27 12:04:22 +00:00
waivers [dv] Add more code coverage waivers 2022-11-18 17:18:24 +00:00
yaml Tweak questa timescale argument 2024-01-08 11:03:10 +00:00
.gitignore [dv] Made dedicated gitignore file and add coverage files 2022-08-19 11:39:49 +01:00
__init__.py core_ibex dv build system refactor 2022-08-16 14:41:12 +01:00
cover.cfg Reorganize ibex dv files (#618) 2020-02-20 15:56:40 -08:00
ibex_dv.f [rtl] Harden lockstep enable against FI 2024-01-23 09:14:45 +00:00
ibex_dv_cosim_dpi.f [dv] Add co-simulation environment support to UVM testbench 2021-10-15 11:30:35 +01:00
Makefile Move 'clean' to top-level makefile 2023-02-08 13:05:59 +00:00
README.md [dv] Add README for Ibex DV 2022-08-03 15:06:03 +01:00
vcs.tcl Explicitly pass directory for waves to VCS's UCLI TCL 2020-03-13 14:18:55 +00:00
wrapper.mk [dv] Refactor reporting and add additional reports 2023-03-03 18:24:58 +00:00

DV for the ibex core

For detailed documention on how Ibex's verification works, please have a look at the dedicated documentation page. This README provides a quick start guide to get things running.

Prerequisites

You need to have Xcelium available on your machine. You can check whether you have it available by running: xrun --verison

You also need Spike to be able to compare to in the cosimulation. We use a lowRISC specific Spike which you can find on its own GitHub page. Some quick build instructions from within the riscv-isa-sim repo:

mkdir build
cd build
../configure --enable-commitlog --enable-misaligned --prefix=$SPIKE_INSTALL_DIR
make
make install
export SPIKE_PATH=$SPIKE_INSTALL_DIR/bin
export PKG_CONFIG_PATH=$PKG_CONFIG_PATH:$SPIKE_INSTALL_DIR/lib/pkgconfig

You will need the RISC-V toolchain. You'll need to add this to your path and then also set the following environment variables:

export RISCV_GCC=riscv32-unknown-elf-gcc
export RISCV_OBJCOPY=riscv32-unknown-elf-objcopy

Running tests

To run tests you can make variations of the following command, where you replace $TEST_NAME with the test (or a series of comma-separated tests) that you would like to run as specified in dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml:

make --keep-going IBEX_CONFIG=opentitan SIMULATOR=xlm ISS=spike ITERATIONS=1 SEED=1 TEST=$TEST_NAME WAVES=0 COV=0