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Pascal Nasahl 8ec0c6f18e [rtl] Harden lockstep enable against FI Currently, the dual-core lockstep FI mitigation is enabled/disabled using a single bit. For transient bit-flips, this is not problematic, as one bit-flip into this signal and one bit into the Ibex is required to threaten the security of the system. However, a permanent stuck-at-0 fault could disable the lockstep completely by targeting this signal. Then, only a single, additional fault (transient or permanent) is required. This PR enhances the FI resilience of the Ibex lockstep by encoding this single bit into a ibex_mubi_t signal, i.e., a 4-bit multi-bit signal. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>	2024-01-23 09:14:45 +00:00
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core_ibex_tb_top.sv	[rtl] Harden lockstep enable against FI	2024-01-23 09:14:45 +00:00

Pascal Nasahl 8ec0c6f18e [rtl] Harden lockstep enable against FI

Currently, the dual-core lockstep FI mitigation is enabled/disabled
using a single bit.
For transient bit-flips, this is not problematic, as one bit-flip
into this signal and one bit into the Ibex is required to threaten
the security of the system.

However, a permanent stuck-at-0 fault could disable the lockstep
completely by targeting this signal. Then, only a single, additional
fault (transient or permanent) is required.

This PR enhances the FI resilience of the Ibex lockstep by encoding
this single bit into a ibex_mubi_t signal, i.e., a 4-bit multi-bit
signal.

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>

2024-01-23 09:14:45 +00:00

core_ibex_tb_top.sv

[rtl] Harden lockstep enable against FI

2024-01-23 09:14:45 +00:00