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An IRQ asserting then deasserting when not explictly cleared by an interrupt handler can lead to RTL/cosim mismatches in some cases. Increasing the delay here minimises those instances. |
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core_ibex_base_test.sv | ||
core_ibex_new_seq_lib.sv | ||
core_ibex_report_server.sv | ||
core_ibex_seq_lib.sv | ||
core_ibex_test_lib.sv | ||
core_ibex_test_pkg.sv | ||
core_ibex_vseq.sv |