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a0c5f5e4d3
This initialisation causes Xcelium to complain about multiple drivers for the variable. Which is rather confusing, but we don't actually need to initialise it: the variable will be X at the start of time, so the logic that stops the simulation if it gets big won't fire until after reset anyway.
98 lines
2.4 KiB
Systemverilog
98 lines
2.4 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Module for communicating with the simulator that interfaces via the memory
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* system.
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*
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* Contains two registers
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*
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* * 0x0 - CHAR_OUT_ADDR - [7:0] of write data output via output_char DPI call
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* and SimOutputManager (see dv/common/cpp/sim_output_manager.cc)
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*
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* * 0x8 - SIM_CTRL_ADDR - Write 1 to bit 0 to halt sim
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*
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* The slightly odd spacing is because we also use SIM_CTRL_ADDR when
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* simulating simple_system code with Spike, which requires the address to be
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* 64-bit aligned.
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*
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*/
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module simulator_ctrl #(
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// passed to simulator via log_name of output_char DPI call
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parameter string LogName = "ibex_out.log",
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// If set flush on every char (useful for monitoring output whilst
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// simulation is running).
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parameter bit FlushOnChar = 1
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) (
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input clk_i,
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input rst_ni,
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input req_i,
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input we_i,
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input [ 3:0] be_i,
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input [31:0] addr_i,
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input [31:0] wdata_i,
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output logic rvalid_o,
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output logic [31:0] rdata_o
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);
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localparam logic [7:0] CHAR_OUT_ADDR = 8'h0;
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localparam logic [7:0] SIM_CTRL_ADDR = 8'h2;
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logic [7:0] ctrl_addr;
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logic [2:0] sim_finish;
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integer log_fd;
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initial begin
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log_fd = $fopen(LogName, "w");
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end
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final begin
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$fclose(log_fd);
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end
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assign ctrl_addr = addr_i[9:2];
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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rvalid_o <= 0;
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sim_finish <= 'b0;
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end else begin
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// Immeditely respond to any request
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rvalid_o <= req_i;
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if (req_i & we_i) begin
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case (ctrl_addr)
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CHAR_OUT_ADDR: begin
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if (be_i[0]) begin
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$fwrite(log_fd, "%c", wdata_i[7:0]);
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if(FlushOnChar) begin
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$fflush(log_fd);
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end
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end
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end
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SIM_CTRL_ADDR: begin
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if ((be_i[0] & wdata_i[0]) && (sim_finish == 'b0)) begin
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$display("Terminating simulation by software request.");
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sim_finish <= 3'b001;
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end
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end
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default: ;
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endcase
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end
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end
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if (sim_finish != 'b0) begin
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sim_finish <= sim_finish + 1;
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end
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if (sim_finish >= 3'b010) begin
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$finish;
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end
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end
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assign rdata_o = '0;
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endmodule
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