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Greg Chadwick 71683aa595 Update lowrisc_ip to lowRISC/opentitan@e0c4026501 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
e0c40265019aa0c74e6903d3b3a144c48a3815ec

* [prim/lint] Fix long line lint error in prim_intr_hw (Alexander
  Williams)
* [csr_seq_lib] Avoid slicing a queue (Rupert Swarbrick)
* [dv] Make mem_model's compare_byte function less chatty (Rupert
  Swarbrick)
* [doc,prim] Improve comments in prim_intr_hw (Harry Callahan)
* [dvsim] Format FormalCfg code. (Miguel Osorio)
* [dvsim] Add results_server dependency to FormalCfg (Miguel Osorio)
* [prim_sha2] Add `hash_running_o` (Andreas Kurth)
* [prim_sha2] Add `hash_continue_i` (Andreas Kurth)
* [prim_sha2] Make digest writable from input while disabled (Andreas
  Kurth)
* [dv,random_reset] Enhance handling of random resets (Guillermo
  Maturana)
* [dv] Change implementation of special mubi access modes (Michael
  Schaffner)
* [dv,cov_merge] Do serial coverage merge for vcs (Guillermo Maturana)
* [dv/csr_utils] Change csr_peek to return the peeked value (Rupert
  Swarbrick)
* [dv/csr_utils] Expand a documentation comment in csr_peek (Rupert
  Swarbrick)
* [dv/csr_utils] Simplify HDL path checking in csr_peek (Rupert
  Swarbrick)
* [dv/csr_utils] Use DV_CHECK to simplify code structure in csr_peek
  (Rupert Swarbrick)
* [dv/csr_utils] Fix a seeming typo in csr_peek (Rupert Swarbrick)
* [dv/csr_utils] Change `csr_peek` to function (Andreas Kurth)
* [prim] Fix lint error in shadow register subreg primitive (Pirmin
  Vogel)
* [otp_ctrl] Add second HW_CFG partition (Michael Schaffner)
* [primgen] Fix parameters in a primgen template (Rupert Swarbrick)
* [prim] Avoid unnecessary Impl parameter in prim_onehot_check (Rupert
  Swarbrick)
* [hw,prim,sha2] Fix syntax error in waiver file (Robert Schilling)
* [prim_sha2,rtl] prim_sha2 minor RTL and styling fixes (Ghada
  Dessouky)
* [prim_sha2,rtl] Add RTL implementation + update core + lint waivers
  (Ghada Dessouky)
* [otp_ctrl] Remove entropy_src chicken switches (Michael Schaffner)
* [dv] Correct direct prediction of regwen (Michael Schaffner)
* [clkmgr] Restructure division clock feedback (Michael Schaffner)
* Revert "[edn] Move prim_edn_req out of prim" (Rupert Swarbrick)
* [rtl, prim] Add 'commit' functionality to prim_count (Greg Chadwick)
* [prim] Fix up 1r1w cores (Alexander Williams)
* [prim] Add two-port memory ECC wrappers (Michael Schaffner)
* [prim] Add two-port memory implementation (Michael Schaffner)
* [prim] Make copies of dual port memory files (Michael Schaffner)
* [otp_ctrl] Add support for multiple HW_CFG partitions (Michael
  Schaffner)
* [otp_ctrl] Add option to disable integrity on a partition (Michael
  Schaffner)
* [dv] Enhance RAL model with clearable mubi types (Michael Schaffner)

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
2024-03-01 10:18:25 +00:00
..
eembc_coremark Update eembc_coremark to eembc/coremark@0c91314 2020-03-09 14:41:40 +00:00
google_riscv-dv Update google_riscv-dv to chipsalliance/riscv-dv@71666eb 2023-10-03 13:42:54 +00:00
lowrisc_ip Update lowrisc_ip to lowRISC/opentitan@e0c4026501 2024-03-01 10:18:25 +00:00
patches [dv,vendor] Pin bitstring version to fix gen_csr_test.py 2023-10-03 13:42:54 +00:00
riscv-arch-tests added exclude files, patch dir and updated riscv-arch-test vendored repo 2023-02-21 14:19:01 +00:00
riscv-isa-sim Update riscv-isa-sim to lowrisc/riscv-isa-sim@a4b823a1 2023-07-18 08:34:09 +00:00
riscv-test-env updated the patch for riscv-test-env 2023-02-21 14:19:01 +00:00
riscv-tests vendored riscv-tests 2023-02-08 13:05:59 +00:00
eembc_coremark.lock.hjson Update eembc_coremark to eembc/coremark@0c91314 2020-03-09 14:41:40 +00:00
google_riscv-dv.lock.hjson Update google_riscv-dv to chipsalliance/riscv-dv@71666eb 2023-10-03 13:42:54 +00:00
google_riscv-dv.vendor.hjson [vendor] Use new RISCV-DV URL 2023-07-18 08:40:01 +00:00
lowrisc_ip.lock.hjson Update lowrisc_ip to lowRISC/opentitan@e0c4026501 2024-03-01 10:18:25 +00:00
lowrisc_ip.vendor.hjson [vendor] Minor alignment improvement 2023-07-06 07:55:47 +00:00
riscv_arch_tests.lock.hjson added exclude files, patch dir and updated riscv-arch-test vendored repo 2023-02-21 14:19:01 +00:00
riscv_arch_tests.vendor.hjson added exclude files, patch dir and updated riscv-arch-test vendored repo 2023-02-21 14:19:01 +00:00
riscv_isa_sim.lock.hjson Update riscv-isa-sim to lowrisc/riscv-isa-sim@a4b823a1 2023-07-18 08:34:09 +00:00
riscv_isa_sim.vendor.hjson [vendor] Use lowRISC repo for vendoring 2023-07-18 08:34:09 +00:00
riscv_test_env.lock.hjson updated the patch for riscv-test-env 2023-02-21 14:19:01 +00:00
riscv_test_env.vendor.hjson updated the patch for riscv-test-env 2023-02-21 14:19:01 +00:00
riscv_tests.lock.hjson excluding env submodule in vendored riscv-tests as riscv-test-env is vendored separately 2023-02-21 14:19:01 +00:00
riscv_tests.vendor.hjson excluding env submodule in vendored riscv-tests as riscv-test-env is vendored separately 2023-02-21 14:19:01 +00:00