mirror of
https://github.com/lowRISC/ibex.git
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90a81a3cc7
Update code from upstream repository https://github.com/lowRISC/opentitan to revision f9e6675507fdd81e0b0dd3481c0a4bca634f322d * [ralgen] Minor correction in alias-file passing mechanism (Michael Schaffner) * [entropy_src/dv] Track FW_OV FIFO exceptions (Martin Lueker-Boden) * [dv/clkmgr] Fix reset handling (Guillermo Maturana) * [flash_ctrl] Add generic registers for the flash wrapper (Michael Schaffner) * [fpv/prim_onehot_check] Fix prim_onehot_check compile error (Cindy Chen) * [dvsim] Minor cleanup of job_runtime updates (Srikrishna Iyer) * [chip/dv] replace wait with DV_WAIT (Weicai Yang) * [dv] Add DV_WAIT macro (Weicai Yang) * [dvsim] Display max CPU time in regression result (Cindy Chen) * [dv, xcelium] Indicate SVA-disabled hierarchies (Srikrishna Iyer) * [dv, xcelium] Update switches, sim finishi (Srikrishna Iyer) * [utils,dvsim] Add wall-clock timeout feature (Guillermo Maturana) * [prim_count] This reworks the primitive to make it more generic (Michael Schaffner) * [dvsim] remove unecessary `sw_build_dir` parameter (Timothy Trippel) * [dvsim] use Bazel labels for SW images (Timothy Trippel) * [entropy_src/dv] Refactor entropy_src_rng_vseq (Martin Lueker-Boden) * [dv, waves] Improve wave dumping (Srikrishna Iyer) * [dv/kmac] Fix EDN timeout assertion failures (Cindy Chen) * [doc] Move style guides into a separate section (Miguel Osorio) * [spi_device/dv] Enable testing SFDP command (Weicai Yang) * [doc] Unlist dangling pages from menus. (Miguel Osorio) * [doc] Add DV intermediate sections (Miguel Osorio) * [doc] Skip markdown templates from the build (Miguel Osorio) * [dv/verilator] Fix numeric base of simulation statistics (Andreas Kurth) * [dvsim] Make email.html filename more descriptive (Srikrishna Iyer) * [csrng/dv] Add deposit to force states when disabled (Steve Nelson) * fix(rdc): typo (Eunchan Kim) * fix(rdc): Include NEW violations only to report (Eunchan Kim) * [dvsim] Add support for SW (bazel) build opts (Srikrishna Iyer) * fix(cdc): Parse NEW violations only (Eunchan Kim) * feat(rdc): Add Meridian RDC log parser (Eunchan Kim) * feat(rdc): Add Meridian RDC flow to dvsim (Eunchan Kim) * [dv/cip_base] Add checking in stress_all_with_rand_reset seq (Cindy Chen) * [clkmgr/prim] Make frequency measurement disable more robust (Timothy Chen) * [prim/lint] Update waivers (Michael Schaffner) * [doc] Update D2 checklist (Michael Schaffner) * [clang-format] Format all covered files (Alexander Williams) * [dvsim] Indicate what is currently running (Srikrishna Iyer) * [doc] Fix trailing whitespace on md files. (Miguel Osorio) * [doc] Remove README.md files from hw,utils folders (Miguel Osorio) * [tools/dv] Modify common.ccf file for proper expression coverage (Steve Nelson) * [prim_edn_req] Accumulate repetition errors until the data is consumed (Pirmin Vogel) * [chip dv] Cleanup task invoked in func warning (Srikrishna Iyer) * [topgen] Pass alias register paths into topgen for top RAL generation (Michael Schaffner) * [dv] Split debug_access opt to another hjson variable for override (Weicai Yang) * [dv] Fix ping exclusion (Weicai Yang) * [prim] update register CDC scheme (Timothy Chen) * [dv] Add assertion to check reg_we onehot error leads to a fatal alert (Weicai Yang) * [sw,tests] Test flash_ctrl init and scramble (Dave Williams) * [PRIM] new clock mux to prevent a glitch (Joshua Park) * [dv] Add prim_cdc_rand_delay exclusion in cover_reg_top (Weicai Yang) * [prim] Add additional qualification to the trigger (Timothy Chen) * [prim] Add description to parameters (Timothy Chen) * [sw,tests] Add -f option to copy in sim.mk (Dave Williams) * [top/spi_device] constraint and clock updates (Timothy Chen) * [dv] Update xcelium coverage config file (Weicai Yang) * fix(prim): High memory usage of Assertion (Eunchan Kim) * [top,dv] rv_dm agent update (Jaedon Kim) * [dv] Enable reg_wr_check test for all blocks (Weicai Yang) * [dv] Update tl testplan for reg write enable check (Weicai Yang) * Refixed 12236 to a more rubust solution (Rasmus Madsen) * [fpv/alert_handler] Add sec_cm FPV testbench for alert_handler (Cindy Chen) * [dv,ralgen] revert `ralgen.py` to use relative file paths (Timothy Trippel) * [dv,ralgen] update `ralgen.py` to use git paths over relative (Timothy Trippel) * doc(prim): Specify ICEBOX for prim_packer (Eunchan Kim) * [bazel,dvsim] update dvsim.py to use Bazel to build SW (Timothy Trippel) * [prim] Added generic xnor2 (Arnon Sharlin) * [flash_ctrl/prim_flash] Add parameters to tweak module latency (Timothy Chen) * [prim_assert] Fix ASSERT_FPV_LINEAR_FSM (Guillermo Maturana) * [chip,rstmgr,dv] regression fix rstmgr_alert_info test (Jaedon Kim) * [dv/tool] Collect csr assertion cov (Cindy Chen) * [otp_ctrl] Add generic registers for prim_otp_wrapper (Michael Schaffner) * [dvsim] Use leaf most field if conflict rather than Exception (Eunchan Kim) * [regtool] Extend UVM backend to support alias definitions (Michael Schaffner) * [fvp/pwrmgr] Pwrmgr fsm error (Cindy Chen) * [dvsim] Revert lowRISC/opentitan#12761 to build SW with meson (Timothy Trippel) * [bazel,dvsim] update dvsim.py to use Bazel to build SW (Timothy Trippel) * [prim] removed unused files (Timothy Chen) * [flash_ctrl] Harden FIFO pointers (Timothy Chen) * [dv] Remove TB_LINT_PASS in all IP checklists (Weicai Yang) * [dv/flash_ctrl] Temp fix flash_ctrl regression compile error (Cindy Chen) * fix(prim): Lint fix for line length (Eunchan Kim) * fix(prim): Lint warning for `err_o` (Eunchan Kim) * [dv] Fix Xcelium toggle collection (Weicai Yang) * [hw/ip] Add extra prim_fifo_sync port (Timothy Chen) * [prim/fifo] Add option to harden prim fifo pointers (Timothy Chen) * [dv_base_reg] Extend search by name functions (Michael Schaffner) * [fpv/lc_ctrl] Add gating conditions for sec_cm assertions (Cindy Chen) * [primgen] Sort the parameters (Weicai Yang) * [python] flake8 lint cleanups (Michael Schaffner) * [prim_subreg] Remove anchor bufs since they are not needed (Michael Schaffner) * [dv] Add `-xprop=mmsopt` run-opt for VCS (Weicai Yang) * [dv] Temporarily remove CDC assertions (Weicai Yang) * [hw/dv] further updated dv flow to now score systemverilog tasks and functions (Rasmus Madsen) * [dv/chip] Fix bit_bash timeout error (Cindy Chen) * [flash_ctrl] Allow fixed priority arbiter (Timothy Chen) * [prim_assert] Minor rewording in comment (Michael Schaffner) * [dv/xcelium] 1 attempt of cleaning up the coverage files (Rasmus Madsen) * [dvsim] revert lowRISC/opentitan#12319 to fix CI (Timothy Trippel) * [primgen] Sort the parameters to ensure stable order (Weicai Yang) * [prim] Fix python style (Weicai Yang) * [bazel] update dvsim.py to build ROMs with bazel (Timothy Trippel) * [dvsim] Correct argparse usage statement and help (Drew Macrae) * [prim_assert] Fix assertion include order (Michael Schaffner) * [ast] Lint fixes and waiver updates (Michael Schaffner) * [prim/lc_ctrl] Create a common assertion macro for linear FSM check (Michael Schaffner) * [dv/csr_utils] Clean up mem_rd/wr print out message (Cindy Chen) * [doc] Update D3 checklist per RFC (Michael Schaffner) * [prim_dom_and_2share] Allow re-use of intermediate results for remasking (Pirmin Vogel) * [prim_dom_and_2share] Add parameter to enable full/optional pipelining (Pirmin Vogel) * [dv/vcs] Update cdc exclusion keyword (Cindy Chen) * [prim] Add a duplicated prim_arbiter instance (Timothy Chen) * [dv/cdc assertion] Temp remove CDC assertion cov collection in VCS (Cindy Chen) * [prim_onehot_check] Rework lint fix (Michael Schaffner) * [mubi/lc_ctrl] Change MUBI / lc_tx_t encodings (Michael Schaffner) * [dv] Update xcelium cover.ccf to only enable coverage for dut (Weicai Yang) * [dv/xcelium] Fix Xcelium nightly regression error (Cindy Chen) * [prim_onehot_mux] Add lint waivers (Michael Schaffner) * [prim_lc_sender] Add waiver (Michael Schaffner) * [prim_mubi] Make sure waiver file is listed in core file (Michael Schaffner) * [tlul_fifo_async] Move waiver to correct file and remove old waivers (Michael Schaffner) * [prim_blanker] Remove prim_and2 waiver file (Michael Schaffner) * [prim_packer] Lint fixes (Michael Schaffner) * [prim_secded] Add lint waiver file (Michael Schaffner) * [dv/cov] Exclude CDC module from collecting coverage (Cindy Chen) * [reggen] Add spurious WE check to autogen'd regfile (Michael Schaffner) * [prim_reg_we_check] Add spurious CSR write checker (Michael Schaffner) * [prim_onehot_check] Add option for permissive en_i checks (Michael Schaffner) * [tools/dv] updated UNR flow to support xcelium/jg (Rasmus Madsen) * [prim] Add dv_macros missing dependency (Timothy Chen) * [top, dv] Fix ext clk plusarg (Weicai Yang) * [dv/build_seed] Fix build_seed (Cindy Chen) * [clkmgr] Correct the disable condition (Timothy Chen) * [flash, dv] Fix RMA test backdoor symbol overwrite (Weicai Yang) * [top, dv] Fix rom backdoor symbol overwrite (Weicai Yang) * [flash_ctrl] Add checks for unexpected acks (Timothy Chen) * [prim_present] Add Verilator lint waiver (Michael Schaffner) * [xcelium] Pass cov_merge_db_dir through to cov_report.tcl (Rupert Swarbrick) * [dv/build_seed] Fix build seed errors (Cindy Chen) * [prim_mubi] Add assertion to check that the values are complementary (Michael Schaffner) Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
52 lines
1.6 KiB
Tcl
52 lines
1.6 KiB
Tcl
# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# Common TCL script invoked at run-time by the simulator.
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# VCS syntax: -ucli -do <this file>
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# Xcelium syntax: -input <this file>
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set dv_root ""
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if {[info exists ::env(dv_root)]} {
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set dv_root "$::env(dv_root)"
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} else {
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puts "ERROR: Script run without dv_root environment variable."
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quit
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}
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# Dumping waves in specific hierarchies.
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#
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# By default, if wave dumping is enabled, all hierarchies of the top level testbench are dumped.
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# For large designs, this may slow down the simulation considerably. To bypass this and only enable
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# waves in specific hierarchies, set the dump_tb_top flag to 0 (i.e. uncomment the line below), and
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# specify the paths to dump on line 32.
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# set dump_tb_top 0
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source "${dv_root}/tools/common.tcl"
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source "${dv_root}/tools/waves.tcl"
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global waves
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global simulator
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global tb_top
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# Dumping waves in specific hierarchies (example):
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# wavedumpScope $waves $simulator tb.dut.foo.bar 12
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# wavedumpScope $waves $simulator tb.dut.baz 0
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if {$simulator eq "xcelium"} {
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puts "INFO: The following assertions are permamently disabled:"
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assertion -list -depth all -multiline -permoff $tb_top
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}
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# In GUI mode, let the user take control of running the simulation.
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global gui
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if {$gui == 0} {
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run
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if {$simulator eq "xcelium"} {
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# Xcelium provides a `finish` tcl command instead of `quit`. The argument '2' enables the
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# logging of additional resource usage information.
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finish 2
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} else {
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quit
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}
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}
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