mirror of
https://github.com/lowRISC/ibex.git
synced 2025-04-24 05:47:36 -04:00
298c8789da
Previously Ibex signalled a major alert on an integrity error (where incoming read data doesn't match its integrity bits) for both read and write responses. This was removed as the data part of a response to a write is ignored. This brings it back in a more measured way. This provides a little extra fault injection hardening as an attacker glitching the memory bus will generate an alert on both read and write responses.
624 lines
22 KiB
Systemverilog
624 lines
22 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Load Store Unit
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*
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* Load Store Unit, used to eliminate multiple access during processor stalls,
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* and to align bytes and halfwords.
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*/
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`include "prim_assert.sv"
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`include "dv_fcov_macros.svh"
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module ibex_load_store_unit #(
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parameter bit MemECC = 1'b0,
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parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32
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) (
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input logic clk_i,
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input logic rst_ni,
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// data interface
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output logic data_req_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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input logic data_bus_err_i,
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input logic data_pmp_err_i,
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output logic [31:0] data_addr_o,
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output logic data_we_o,
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output logic [3:0] data_be_o,
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output logic [MemDataWidth-1:0] data_wdata_o,
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input logic [MemDataWidth-1:0] data_rdata_i,
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// signals to/from ID/EX stage
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input logic lsu_we_i, // write enable -> from ID/EX
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input logic [1:0] lsu_type_i, // data type: word, half word, byte -> from ID/EX
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input logic [31:0] lsu_wdata_i, // data to write to memory -> from ID/EX
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input logic lsu_sign_ext_i, // sign extension -> from ID/EX
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output logic [31:0] lsu_rdata_o, // requested data -> to ID/EX
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output logic lsu_rdata_valid_o,
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input logic lsu_req_i, // data request -> from ID/EX
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input logic [31:0] adder_result_ex_i, // address computed in ALU -> from ID/EX
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output logic addr_incr_req_o, // request address increment for
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// misaligned accesses -> to ID/EX
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output logic [31:0] addr_last_o, // address of last transaction -> to controller
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// -> mtval
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// -> AGU for misaligned accesses
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output logic lsu_req_done_o, // Signals that data request is complete
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// (only need to await final data
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// response) -> to ID/EX
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output logic lsu_resp_valid_o, // LSU has response from transaction -> to ID/EX
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// exception signals
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output logic load_err_o,
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output logic load_resp_intg_err_o,
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output logic store_err_o,
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output logic store_resp_intg_err_o,
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output logic busy_o,
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output logic perf_load_o,
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output logic perf_store_o
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);
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logic [31:0] data_addr;
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logic [31:0] data_addr_w_aligned;
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logic [31:0] addr_last_q, addr_last_d;
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logic addr_update;
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logic ctrl_update;
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logic rdata_update;
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logic [31:8] rdata_q;
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logic [1:0] rdata_offset_q;
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logic [1:0] data_type_q;
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logic data_sign_ext_q;
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logic data_we_q;
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logic [1:0] data_offset; // mux control for data to be written to memory
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logic [3:0] data_be;
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logic [31:0] data_wdata;
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logic [31:0] data_rdata_ext;
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logic [31:0] rdata_w_ext; // word realignment for misaligned loads
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logic [31:0] rdata_h_ext; // sign extension for half words
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logic [31:0] rdata_b_ext; // sign extension for bytes
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logic split_misaligned_access;
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logic handle_misaligned_q, handle_misaligned_d; // high after receiving grant for first
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// part of a misaligned access
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logic pmp_err_q, pmp_err_d;
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logic lsu_err_q, lsu_err_d;
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logic data_intg_err, data_or_pmp_err;
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typedef enum logic [2:0] {
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IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT,
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WAIT_RVALID_MIS_GNTS_DONE
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} ls_fsm_e;
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ls_fsm_e ls_fsm_cs, ls_fsm_ns;
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assign data_addr = adder_result_ex_i;
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assign data_offset = data_addr[1:0];
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///////////////////
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// BE generation //
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///////////////////
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always_comb begin
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unique case (lsu_type_i) // Data type 00 Word, 01 Half word, 11,10 byte
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2'b00: begin // Writing a word
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if (!handle_misaligned_q) begin // first part of potentially misaligned transaction
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unique case (data_offset)
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2'b00: data_be = 4'b1111;
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2'b01: data_be = 4'b1110;
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2'b10: data_be = 4'b1100;
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2'b11: data_be = 4'b1000;
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default: data_be = 4'b1111;
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endcase // case (data_offset)
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end else begin // second part of misaligned transaction
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unique case (data_offset)
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2'b00: data_be = 4'b0000; // this is not used, but included for completeness
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2'b01: data_be = 4'b0001;
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2'b10: data_be = 4'b0011;
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2'b11: data_be = 4'b0111;
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default: data_be = 4'b1111;
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endcase // case (data_offset)
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end
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end
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2'b01: begin // Writing a half word
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if (!handle_misaligned_q) begin // first part of potentially misaligned transaction
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unique case (data_offset)
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2'b00: data_be = 4'b0011;
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2'b01: data_be = 4'b0110;
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2'b10: data_be = 4'b1100;
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2'b11: data_be = 4'b1000;
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default: data_be = 4'b1111;
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endcase // case (data_offset)
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end else begin // second part of misaligned transaction
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data_be = 4'b0001;
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end
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end
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2'b10,
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2'b11: begin // Writing a byte
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unique case (data_offset)
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2'b00: data_be = 4'b0001;
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2'b01: data_be = 4'b0010;
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2'b10: data_be = 4'b0100;
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2'b11: data_be = 4'b1000;
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default: data_be = 4'b1111;
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endcase // case (data_offset)
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end
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default: data_be = 4'b1111;
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endcase // case (lsu_type_i)
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end
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/////////////////////
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// WData alignment //
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/////////////////////
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// prepare data to be written to the memory
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// we handle misaligned accesses, half word and byte accesses here
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always_comb begin
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unique case (data_offset)
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2'b00: data_wdata = lsu_wdata_i[31:0];
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2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]};
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2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]};
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2'b11: data_wdata = {lsu_wdata_i[ 7:0], lsu_wdata_i[31: 8]};
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default: data_wdata = lsu_wdata_i[31:0];
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endcase // case (data_offset)
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end
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/////////////////////
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// RData alignment //
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/////////////////////
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// register for unaligned rdata
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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rdata_q <= '0;
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end else if (rdata_update) begin
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rdata_q <= data_rdata_i[31:8];
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end
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end
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// registers for transaction control
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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rdata_offset_q <= 2'h0;
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data_type_q <= 2'h0;
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data_sign_ext_q <= 1'b0;
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data_we_q <= 1'b0;
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end else if (ctrl_update) begin
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rdata_offset_q <= data_offset;
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data_type_q <= lsu_type_i;
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data_sign_ext_q <= lsu_sign_ext_i;
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data_we_q <= lsu_we_i;
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end
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end
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// Store last address for mtval + AGU for misaligned transactions. Do not update in case of
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// errors, mtval needs the (first) failing address. Where an aligned access or the first half of
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// a misaligned access sees an error provide the calculated access address. For the second half of
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// a misaligned access provide the word aligned address of the second half.
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assign addr_last_d = addr_incr_req_o ? data_addr_w_aligned : data_addr;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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addr_last_q <= '0;
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end else if (addr_update) begin
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addr_last_q <= addr_last_d;
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end
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end
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// take care of misaligned words
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always_comb begin
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unique case (rdata_offset_q)
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2'b00: rdata_w_ext = data_rdata_i[31:0];
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2'b01: rdata_w_ext = {data_rdata_i[ 7:0], rdata_q[31:8]};
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2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]};
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2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]};
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default: rdata_w_ext = data_rdata_i[31:0];
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endcase
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end
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////////////////////
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// Sign extension //
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////////////////////
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// sign extension for half words
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always_comb begin
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unique case (rdata_offset_q)
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2'b00: begin
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if (!data_sign_ext_q) begin
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rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
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end else begin
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rdata_h_ext = {{16{data_rdata_i[15]}}, data_rdata_i[15:0]};
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end
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end
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2'b01: begin
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if (!data_sign_ext_q) begin
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rdata_h_ext = {16'h0000, data_rdata_i[23:8]};
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end else begin
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rdata_h_ext = {{16{data_rdata_i[23]}}, data_rdata_i[23:8]};
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end
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end
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2'b10: begin
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if (!data_sign_ext_q) begin
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rdata_h_ext = {16'h0000, data_rdata_i[31:16]};
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end else begin
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rdata_h_ext = {{16{data_rdata_i[31]}}, data_rdata_i[31:16]};
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end
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end
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2'b11: begin
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if (!data_sign_ext_q) begin
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rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]};
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end else begin
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rdata_h_ext = {{16{data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]};
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end
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end
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default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
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endcase // case (rdata_offset_q)
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end
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// sign extension for bytes
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always_comb begin
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unique case (rdata_offset_q)
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2'b00: begin
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if (!data_sign_ext_q) begin
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rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]};
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end else begin
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rdata_b_ext = {{24{data_rdata_i[7]}}, data_rdata_i[7:0]};
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end
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end
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2'b01: begin
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if (!data_sign_ext_q) begin
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rdata_b_ext = {24'h00_0000, data_rdata_i[15:8]};
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end else begin
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rdata_b_ext = {{24{data_rdata_i[15]}}, data_rdata_i[15:8]};
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end
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end
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2'b10: begin
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if (!data_sign_ext_q) begin
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rdata_b_ext = {24'h00_0000, data_rdata_i[23:16]};
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end else begin
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rdata_b_ext = {{24{data_rdata_i[23]}}, data_rdata_i[23:16]};
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end
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end
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2'b11: begin
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if (!data_sign_ext_q) begin
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rdata_b_ext = {24'h00_0000, data_rdata_i[31:24]};
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end else begin
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rdata_b_ext = {{24{data_rdata_i[31]}}, data_rdata_i[31:24]};
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end
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end
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default: rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]};
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endcase // case (rdata_offset_q)
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end
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// select word, half word or byte sign extended version
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always_comb begin
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unique case (data_type_q)
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2'b00: data_rdata_ext = rdata_w_ext;
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2'b01: data_rdata_ext = rdata_h_ext;
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2'b10,2'b11: data_rdata_ext = rdata_b_ext;
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default: data_rdata_ext = rdata_w_ext;
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endcase // case (data_type_q)
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end
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///////////////////////////////
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// Read data integrity check //
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///////////////////////////////
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// SEC_CM: BUS.INTEGRITY
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if (MemECC) begin : g_mem_rdata_ecc
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logic [1:0] ecc_err;
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logic [MemDataWidth-1:0] data_rdata_buf;
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prim_buf #(.Width(MemDataWidth)) u_prim_buf_instr_rdata (
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.in_i (data_rdata_i),
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.out_o(data_rdata_buf)
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);
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prim_secded_inv_39_32_dec u_data_intg_dec (
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.data_i (data_rdata_buf),
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.data_o (),
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.syndrome_o (),
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.err_o (ecc_err)
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);
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// Don't care if error is correctable or not, they're all treated the same
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assign data_intg_err = |ecc_err;
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end else begin : g_no_mem_data_ecc
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assign data_intg_err = 1'b0;
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end
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/////////////
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// LSU FSM //
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/////////////
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// check for misaligned accesses that need to be split into two word-aligned accesses
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assign split_misaligned_access =
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((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access
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((lsu_type_i == 2'b01) && (data_offset == 2'b11)); // misaligned half-word access
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// FSM
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always_comb begin
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ls_fsm_ns = ls_fsm_cs;
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data_req_o = 1'b0;
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addr_incr_req_o = 1'b0;
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handle_misaligned_d = handle_misaligned_q;
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pmp_err_d = pmp_err_q;
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lsu_err_d = lsu_err_q;
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addr_update = 1'b0;
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ctrl_update = 1'b0;
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rdata_update = 1'b0;
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perf_load_o = 1'b0;
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perf_store_o = 1'b0;
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unique case (ls_fsm_cs)
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IDLE: begin
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pmp_err_d = 1'b0;
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if (lsu_req_i) begin
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data_req_o = 1'b1;
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pmp_err_d = data_pmp_err_i;
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lsu_err_d = 1'b0;
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perf_load_o = ~lsu_we_i;
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perf_store_o = lsu_we_i;
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if (data_gnt_i) begin
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ctrl_update = 1'b1;
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addr_update = 1'b1;
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handle_misaligned_d = split_misaligned_access;
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ls_fsm_ns = split_misaligned_access ? WAIT_RVALID_MIS : IDLE;
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end else begin
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ls_fsm_ns = split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT;
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end
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end
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end
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WAIT_GNT_MIS: begin
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data_req_o = 1'b1;
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// data_pmp_err_i is valid during the address phase of a request. An error will block the
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// external request and so a data_gnt_i might never be signalled. The registered version
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// pmp_err_q is only updated for new address phases and so can be used in WAIT_GNT* and
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// WAIT_RVALID* states
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if (data_gnt_i || pmp_err_q) begin
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addr_update = 1'b1;
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ctrl_update = 1'b1;
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handle_misaligned_d = 1'b1;
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ls_fsm_ns = WAIT_RVALID_MIS;
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end
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end
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WAIT_RVALID_MIS: begin
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// push out second request
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data_req_o = 1'b1;
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// tell ID/EX stage to update the address
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addr_incr_req_o = 1'b1;
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// first part rvalid is received, or gets a PMP error
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if (data_rvalid_i || pmp_err_q) begin
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// Update the PMP error for the second part
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pmp_err_d = data_pmp_err_i;
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// Record the error status of the first part
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lsu_err_d = data_bus_err_i | pmp_err_q;
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// Capture the first rdata for loads
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rdata_update = ~data_we_q;
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// If already granted, wait for second rvalid
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ls_fsm_ns = data_gnt_i ? IDLE : WAIT_GNT;
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// Update the address for the second part, if no error
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addr_update = data_gnt_i & ~(data_bus_err_i | pmp_err_q);
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// clear handle_misaligned if second request is granted
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handle_misaligned_d = ~data_gnt_i;
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end else begin
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// first part rvalid is NOT received
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if (data_gnt_i) begin
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// second grant is received
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ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE;
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handle_misaligned_d = 1'b0;
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end
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end
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end
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WAIT_GNT: begin
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// tell ID/EX stage to update the address
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addr_incr_req_o = handle_misaligned_q;
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data_req_o = 1'b1;
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if (data_gnt_i || pmp_err_q) begin
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ctrl_update = 1'b1;
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// Update the address, unless there was an error
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addr_update = ~lsu_err_q;
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ls_fsm_ns = IDLE;
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handle_misaligned_d = 1'b0;
|
|
end
|
|
end
|
|
|
|
WAIT_RVALID_MIS_GNTS_DONE: begin
|
|
// tell ID/EX stage to update the address (to make sure the
|
|
// second address can be captured correctly for mtval and PMP checking)
|
|
addr_incr_req_o = 1'b1;
|
|
// Wait for the first rvalid, second request is already granted
|
|
if (data_rvalid_i) begin
|
|
// Update the pmp error for the second part
|
|
pmp_err_d = data_pmp_err_i;
|
|
// The first part cannot see a PMP error in this state
|
|
lsu_err_d = data_bus_err_i;
|
|
// Now we can update the address for the second part if no error
|
|
addr_update = ~data_bus_err_i;
|
|
// Capture the first rdata for loads
|
|
rdata_update = ~data_we_q;
|
|
// Wait for second rvalid
|
|
ls_fsm_ns = IDLE;
|
|
end
|
|
end
|
|
|
|
default: begin
|
|
ls_fsm_ns = IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE);
|
|
|
|
// registers for FSM
|
|
always_ff @(posedge clk_i or negedge rst_ni) begin
|
|
if (!rst_ni) begin
|
|
ls_fsm_cs <= IDLE;
|
|
handle_misaligned_q <= '0;
|
|
pmp_err_q <= '0;
|
|
lsu_err_q <= '0;
|
|
end else begin
|
|
ls_fsm_cs <= ls_fsm_ns;
|
|
handle_misaligned_q <= handle_misaligned_d;
|
|
pmp_err_q <= pmp_err_d;
|
|
lsu_err_q <= lsu_err_d;
|
|
end
|
|
end
|
|
|
|
/////////////
|
|
// Outputs //
|
|
/////////////
|
|
|
|
assign data_or_pmp_err = lsu_err_q | data_bus_err_i | pmp_err_q;
|
|
assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE);
|
|
assign lsu_rdata_valid_o =
|
|
(ls_fsm_cs == IDLE) & data_rvalid_i & ~data_or_pmp_err & ~data_we_q & ~data_intg_err;
|
|
|
|
// output to register file
|
|
assign lsu_rdata_o = data_rdata_ext;
|
|
|
|
// output data address must be word aligned
|
|
assign data_addr_w_aligned = {data_addr[31:2], 2'b00};
|
|
|
|
// output to data interface
|
|
assign data_addr_o = data_addr_w_aligned;
|
|
assign data_we_o = lsu_we_i;
|
|
assign data_be_o = data_be;
|
|
|
|
/////////////////////////////////////
|
|
// Write data integrity generation //
|
|
/////////////////////////////////////
|
|
|
|
// SEC_CM: BUS.INTEGRITY
|
|
if (MemECC) begin : g_mem_wdata_ecc
|
|
prim_secded_inv_39_32_enc u_data_gen (
|
|
.data_i (data_wdata),
|
|
.data_o (data_wdata_o)
|
|
);
|
|
end else begin : g_no_mem_wdata_ecc
|
|
assign data_wdata_o = data_wdata;
|
|
end
|
|
|
|
// output to ID stage: mtval + AGU for misaligned transactions
|
|
assign addr_last_o = addr_last_q;
|
|
|
|
// Signal a load or store error depending on the transaction type outstanding
|
|
assign load_err_o = data_or_pmp_err & ~data_we_q & lsu_resp_valid_o;
|
|
assign store_err_o = data_or_pmp_err & data_we_q & lsu_resp_valid_o;
|
|
// Integrity errors are their own category for timing reasons. load_err_o is factored directly
|
|
// into data_req_o to enable synchronous exception on load errors without performance loss (An
|
|
// upcoming load cannot request until the current load has seen its response, so the earliest
|
|
// point the new request can be sent is the same cycle the response is seen). If load_err_o isn't
|
|
// factored into data_req_o there would have to be a stall cycle between all back to back loads.
|
|
// The data_intg_err signal is generated combinatorially from the incoming data_rdata_i. Were it
|
|
// to be factored into load_err_o there would be a feedthrough path from data_rdata_i to
|
|
// data_req_o which is undesirable.
|
|
assign load_resp_intg_err_o = data_intg_err & data_rvalid_i & ~data_we_q;
|
|
assign store_resp_intg_err_o = data_intg_err & data_rvalid_i & data_we_q;
|
|
|
|
assign busy_o = (ls_fsm_cs != IDLE);
|
|
|
|
//////////
|
|
// FCOV //
|
|
//////////
|
|
`ifndef DV_FCOV_DISABLE
|
|
// Set when awaiting the response for the second half of a misaligned access
|
|
logic fcov_mis_2_en_d, fcov_mis_2_en_q;
|
|
|
|
// fcov_mis_rvalid_1: Set when the response is received to the first half of a misaligned access,
|
|
// fcov_mis_rvalid_2: Set when response is received for the second half
|
|
logic fcov_mis_rvalid_1, fcov_mis_rvalid_2;
|
|
|
|
// Set when the first half of a misaligned access saw a bus errror
|
|
logic fcov_mis_bus_err_1_d, fcov_mis_bus_err_1_q;
|
|
|
|
assign fcov_mis_rvalid_1 = ls_fsm_cs inside {WAIT_RVALID_MIS, WAIT_RVALID_MIS_GNTS_DONE} &&
|
|
data_rvalid_i;
|
|
|
|
assign fcov_mis_rvalid_2 = ls_fsm_cs inside {IDLE} && fcov_mis_2_en_q && data_rvalid_i;
|
|
|
|
assign fcov_mis_2_en_d = fcov_mis_rvalid_2 ? 1'b0 : // clr
|
|
fcov_mis_rvalid_1 ? 1'b1 : // set
|
|
fcov_mis_2_en_q ;
|
|
|
|
assign fcov_mis_bus_err_1_d = fcov_mis_rvalid_2 ? 1'b0 : // clr
|
|
fcov_mis_rvalid_1 && data_bus_err_i ? 1'b1 : // set
|
|
fcov_mis_bus_err_1_q ;
|
|
|
|
always_ff @(posedge clk_i or negedge rst_ni) begin
|
|
if (!rst_ni) begin
|
|
fcov_mis_2_en_q <= 1'b0;
|
|
fcov_mis_bus_err_1_q <= 1'b0;
|
|
end else begin
|
|
fcov_mis_2_en_q <= fcov_mis_2_en_d;
|
|
fcov_mis_bus_err_1_q <= fcov_mis_bus_err_1_d;
|
|
end
|
|
end
|
|
`endif
|
|
|
|
`DV_FCOV_SIGNAL(logic, ls_error_exception, (load_err_o | store_err_o) & ~pmp_err_q)
|
|
`DV_FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q)
|
|
`DV_FCOV_SIGNAL(logic, ls_first_req, lsu_req_i & (ls_fsm_cs == IDLE))
|
|
`DV_FCOV_SIGNAL(logic, ls_second_req,
|
|
(ls_fsm_cs inside {WAIT_GNT, WAIT_RVALID_MIS}) & data_req_o & addr_incr_req_o)
|
|
`DV_FCOV_SIGNAL(logic, ls_mis_pmp_err_1,
|
|
(ls_fsm_cs inside {WAIT_RVALID_MIS, WAIT_GNT_MIS}) && pmp_err_q)
|
|
`DV_FCOV_SIGNAL(logic, ls_mis_pmp_err_2,
|
|
(ls_fsm_cs inside {WAIT_RVALID_MIS, WAIT_RVALID_MIS_GNTS_DONE}) && data_pmp_err_i)
|
|
|
|
////////////////
|
|
// Assertions //
|
|
////////////////
|
|
|
|
// Selectors must be known/valid.
|
|
`ASSERT(IbexDataTypeKnown, (lsu_req_i | busy_o) |-> !$isunknown(lsu_type_i))
|
|
`ASSERT(IbexDataOffsetKnown, (lsu_req_i | busy_o) |-> !$isunknown(data_offset))
|
|
`ASSERT_KNOWN(IbexRDataOffsetQKnown, rdata_offset_q)
|
|
`ASSERT_KNOWN(IbexDataTypeQKnown, data_type_q)
|
|
`ASSERT(IbexLsuStateValid, ls_fsm_cs inside {
|
|
IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT,
|
|
WAIT_RVALID_MIS_GNTS_DONE})
|
|
|
|
// Address must not contain X when request is sent.
|
|
`ASSERT(IbexDataAddrUnknown, data_req_o |-> !$isunknown(data_addr_o))
|
|
|
|
// Address must be word aligned when request is sent.
|
|
`ASSERT(IbexDataAddrUnaligned, data_req_o |-> (data_addr_o[1:0] == 2'b00))
|
|
|
|
endmodule
|