Exact

Exact Union RegExp

Greg Chadwick eca86aef03 [rtl] Fix id_exception_o signal ... Previously it was asserted when an instruction in ID would cause an exception but an earlier instruction in WB also causes an exception which takes priority. This didn't cause a functional bug as the `id_exception_o` signal was used in a single place ORed with `wb_exception_o`. However it was confusing behaviour and could cause killed instructions to appear on the RVFI causing false cosim mismatches.		2022-10-31 14:29:59 +00:00
..
ibex_alu.sv	[lint] Minor fixes	2022-04-12 08:38:35 -07:00
ibex_branch_predict.sv	Fix Xcelium warnings	2020-11-18 10:16:48 +00:00
ibex_compressed_decoder.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_controller.sv	[rtl] Fix id_exception_o signal	2022-10-31 14:29:59 +00:00
ibex_core.f	Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr	2020-03-06 12:49:51 +01:00
ibex_core.sv	[rtl] Protect core_busy_o with a multi-bit encoding	2022-10-25 12:52:01 +02:00
ibex_counter.sv	[rtl] Fix retired instruction counters	2021-09-17 12:28:10 +01:00
ibex_cs_registers.sv	Update SCONTEXT address, add MSCONTEXT csr to match riscv_debug 1.0	2022-10-05 16:59:12 +01:00
ibex_csr.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_decoder.sv	[rtl] Remove redundant comments in decoder	2021-12-16 14:18:00 +01:00
ibex_dummy_instr.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_ex_block.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_fetch_fifo.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_icache.sv	[lint] Make case statements unique case	2022-08-24 15:33:38 -07:00
ibex_id_stage.sv	[rtl] Immediately stop execution when fetch disabled	2022-10-16 17:17:15 +01:00
ibex_if_stage.sv	[if,pmp] Check second bit instead of third for instruction alignment	2022-10-06 10:23:01 +01:00
ibex_load_store_unit.sv	[rtl/dv] Bring back data integrity check on write responses	2022-10-14 18:22:58 +01:00
ibex_lockstep.sv	[rtl] Protect core_busy_o with a multi-bit encoding	2022-10-25 12:52:01 +02:00
ibex_multdiv_fast.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_multdiv_slow.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_pkg.sv	[rtl] Protect core_busy_o with a multi-bit encoding	2022-10-25 12:52:01 +02:00
ibex_pmp.sv	[lint] Minor fixes	2022-08-05 12:25:36 -07:00
ibex_pmp_reset_default.svh	[rtl,doc] Add customisable PMP reset values	2022-01-24 10:01:36 +00:00
ibex_prefetch_buffer.sv	[rtl] Remove "mispredict" ports from prefetch buffer	2022-04-04 16:56:04 +01:00
ibex_register_file_ff.sv	[rtl] Switch FF RF to use unpacked arrays	2022-09-27 09:59:09 +01:00
ibex_register_file_fpga.sv	[regfile] Add countermeasure label	2022-04-13 14:36:52 -07:00
ibex_register_file_latch.sv	[regfile] Add countermeasure label	2022-04-13 14:36:52 -07:00
ibex_top.sv	[rtl] Protect core_busy_o with a multi-bit encoding	2022-10-25 12:52:01 +02:00
ibex_top_tracing.sv	[rtl] Protect core_busy_o with a multi-bit encoding	2022-10-25 12:52:01 +02:00
ibex_tracer.sv	[ibex_tracer] Void cast function calls	2022-01-20 16:59:22 -08:00
ibex_tracer_pkg.sv	[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)	2021-12-06 11:14:49 +01:00
ibex_wb_stage.sv	[rtl] Fix retired instruction counters	2021-09-17 12:28:10 +01:00