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18 lines
683 B
Markdown
18 lines
683 B
Markdown
# zero-riscy: RISC-V Core
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*zero-riscy** is a small 2-stage RISC-V core derived from RI5CY.
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**zero-riscy** fully implements the RV32IMC instruction set and a minimal
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set of RISCV privileged specifications.
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**zero-riscy** can be configured to be very small by disabling the RV32M extensions
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and by activating the RV32E extensios. This configuration is called **micro-riscy**
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The core was developed as part of the [PULP platform](http://pulp.ethz.ch/) for
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energy-efficient computing and is currently used as the control core for
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PULP and PULPino.
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## Documentation
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A datasheet that explains the most important features of the core can be found
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in the `zeroriscy-doc` repository.
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