mirror of
https://github.com/lowRISC/ibex.git
synced 2025-06-28 09:17:17 -04:00
ea4e9383db
Convert `prim_generic_buf` to Verilog as well. Also, replace 'prim_buf' with 'prim_generic_buf' whenever we see a `prim_buf` in a generated Verilog file. Fixes #1557 Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
96 lines
2.6 KiB
Bash
Executable file
96 lines
2.6 KiB
Bash
Executable file
#!/bin/bash
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# This script drives the experimental Ibex synthesis flow. More details can be
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# found in README.md
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set -e
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set -o pipefail
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error () {
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echo >&2 "$@"
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exit 1
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}
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teelog () {
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tee "$LR_SYNTH_OUT_DIR/log/$1.log"
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}
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if [ ! -f syn_setup.sh ]; then
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error "No syn_setup.sh file: see README.md for instructions"
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fi
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#-------------------------------------------------------------------------
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# setup flow variables
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#-------------------------------------------------------------------------
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source syn_setup.sh
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#-------------------------------------------------------------------------
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# use sv2v to convert all SystemVerilog files to Verilog
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#-------------------------------------------------------------------------
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LR_DEP_SOURCES=(
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"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv"
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)
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mkdir -p "$LR_SYNTH_OUT_DIR/generated"
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mkdir -p "$LR_SYNTH_OUT_DIR/log"
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mkdir -p "$LR_SYNTH_OUT_DIR/reports/timing"
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# Convert dependency sources
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for file in ${LR_DEP_SOURCES[@]}; do
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module=`basename -s .sv $file`
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sv2v \
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--define=SYNTHESIS --define=YOSYS \
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-I../vendor/lowrisc_ip/ip/prim/rtl \
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$file \
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> $LR_SYNTH_OUT_DIR/generated/${module}.v
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done
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# Convert core sources
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for file in ../rtl/*.sv; do
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module=`basename -s .sv $file`
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# Skip packages
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if echo "$module" | grep -q '_pkg$'; then
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continue
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fi
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sv2v \
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--define=SYNTHESIS --define=YOSYS \
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../rtl/*_pkg.sv \
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../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv \
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../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv \
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-I../vendor/lowrisc_ip/ip/prim/rtl \
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-I../vendor/lowrisc_ip/dv/sv/dv_utils \
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$file \
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> $LR_SYNTH_OUT_DIR/generated/${module}.v
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# Make sure auto-generated primitives are resolved to generic primitives
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# where available.
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sed -i 's/prim_buf/prim_generic_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
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done
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# remove tracer (not needed for synthesis)
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rm -f $LR_SYNTH_OUT_DIR/generated/ibex_tracer.v
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# remove the FPGA & register-based register file (because we will use the
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# latch-based one instead)
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rm -f $LR_SYNTH_OUT_DIR/generated/ibex_register_file_ff.v
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rm -f $LR_SYNTH_OUT_DIR/generated/ibex_register_file_fpga.v
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yosys -c ./tcl/yosys_run_synth.tcl |& teelog syn || {
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error "Failed to synthesize RTL with Yosys"
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}
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sta ./tcl/sta_run_reports.tcl |& teelog sta || {
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error "Failed to run static timing analysis"
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}
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./translate_timing_rpts.sh
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python/get_kge.py $LR_SYNTH_CELL_LIBRARY_PATH $LR_SYNTH_OUT_DIR/reports/area.rpt
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