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ibex/shared
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Greg Chadwick 2041f10c69 Added simple system 
Simple system is a basic verilator top-level testbench for running
 executables.  It has functionality for outputting text to a log file
 and for the software to terminate the simulation
2019-11-09 07:48:47 +00:00
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rtl Added simple system 2019-11-09 07:48:47 +00:00
sim_shared.core Added simple system 2019-11-09 07:48:47 +00:00