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2041f10c69
Simple system is a basic verilator top-level testbench for running executables. It has functionality for outputting text to a log file and for the software to terminate the simulation
20 lines
497 B
Text
20 lines
497 B
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:sim_shared"
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description: "Collection of useful RTL for building simulations"
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filesets:
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files_sim_sv:
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files:
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- ./rtl/prim_clock_gating.sv
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- ./rtl/ram_1p.sv
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- ./rtl/bus.sv
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- ./rtl/sim/simulator_ctrl.sv
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file_type: systemVerilogSource
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targets:
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default:
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filesets:
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- files_sim_sv
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