Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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2015-04-10 16:03:16 +02:00
include JAL working 2015-04-09 16:09:37 +02:00
alu.sv JAL working 2015-04-09 16:09:37 +02:00
controller.sv JAL working 2015-04-09 16:09:37 +02:00
debug_unit.sv Initial RiscV core commit; still in an early stage, but ALU instructions work 2015-04-01 11:11:07 +02:00
ex_stage.sv JAL working 2015-04-09 16:09:37 +02:00
id_stage.sv JAL working 2015-04-09 16:09:37 +02:00
if_stage.sv JAL working 2015-04-09 16:09:37 +02:00
instr_core_interface.sv JAL working 2015-04-09 16:09:37 +02:00
load_store_unit.sv Initial RiscV core commit; still in an early stage, but ALU instructions work 2015-04-01 11:11:07 +02:00
mult.sv Initial RiscV core commit; still in an early stage, but ALU instructions work 2015-04-01 11:11:07 +02:00
register_file.sv Initial RiscV core commit; still in an early stage, but ALU instructions work 2015-04-01 11:11:07 +02:00
riscv_core.sv Added instruction tracer to riscv core 2015-04-10 16:03:16 +02:00
wb_stage.sv Initial RiscV core commit; still in an early stage, but ALU instructions work 2015-04-01 11:11:07 +02:00