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github-mirrors/ ibex

SystemVerilog 0 0

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucore hardware risc-v rv32

Updated 2025-06-27 07:09:24 -04:00

github-mirrors/ cva6

SystemVerilog 0 0

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

ariane asic cpu fpga risc-v rv64gc systemverilog-hdl

Updated 2025-06-24 18:19:03 -04:00

github-mirrors/ neorv32

VHDL 0 0

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asip axi cpu embedded fpga microcontroller neorv32 on-chip-debbuger processor risc-v riscv rtl rtos rv32 safety soc soft-core system-on-chip verilog vhdl

Updated 2025-06-22 15:11:25 -04:00

github-mirrors/ serv

Verilog 0 0

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Updated 2025-06-05 02:56:43 -04:00

github-mirrors/ harv

VHDL 0 0

HARV - HArdened Risc-V

fault-tolerance fpga processor reliability risc-v rv32i

Updated 2022-03-10 13:29:46 -05:00

github-mirrors/ RPU

VHDL 0 0

Basic RISC-V CPU implementation in VHDL.

apache2-license cpu fpga risc-v riscv vhdl

Updated 2020-09-11 19:23:50 -04:00