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This change has been informed by advice from the lowRISC legal committee. The Solderpad 0.51 license states "the Licensor permits any Work licensed under this License, at the option of the Licensee, to be treated as licensed under the Apache License Version 2.0". We use this freedom to convert license markings to Apache 2.0. This commit ensures that we retain all authorship and copyright attribution information.
472 lines
14 KiB
Systemverilog
472 lines
14 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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////////////////////////////////////////////////////////////////////////////////
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// Engineer: Sven Stucki - svstucki@student.ethz.ch //
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// //
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// Additional contributions by: //
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// Andreas Traber - atraber@iis.ee.ethz.ch //
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// Davide Schiavone - pschiavo@iis.ee.ethz.ch //
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// //
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// Design Name: Control and Status Registers //
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// Project Name: ibex //
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// Language: SystemVerilog //
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// //
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// Description: Control and Status Registers (CSRs) loosely following the //
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// RiscV draft priviledged instruction set spec (v1.9) //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "ibex_config.sv"
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import ibex_defines::*;
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`ifndef PULP_FPGA_EMUL
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`ifdef SYNTHESIS
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`define ASIC_SYNTHESIS
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`endif
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`endif
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module ibex_cs_registers
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#(
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parameter N_EXT_CNT = 0
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)
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(
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// Clock and Reset
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input logic clk,
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input logic rst_n,
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// Core and Cluster ID
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input logic [3:0] core_id_i,
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input logic [5:0] cluster_id_i,
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// Used for boot address
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input logic [23:0] boot_addr_i,
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// Interface to registers (SRAM like)
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input logic csr_access_i,
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input logic [11:0] csr_addr_i,
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input logic [31:0] csr_wdata_i,
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input logic [1:0] csr_op_i,
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output logic [31:0] csr_rdata_o,
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// Interrupts
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output logic m_irq_enable_o,
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output logic [31:0] mepc_o,
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input logic [31:0] pc_if_i,
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input logic [31:0] pc_id_i,
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input logic csr_save_if_i,
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input logic csr_save_id_i,
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input logic csr_restore_mret_i,
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input logic [5:0] csr_cause_i,
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input logic csr_save_cause_i,
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// Performance Counters
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input logic if_valid_i, // IF stage gives a new instruction
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input logic id_valid_i, // ID stage is done
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input logic is_compressed_i, // compressed instruction in ID
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input logic is_decoding_i, // controller is in DECODE state
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input logic imiss_i, // instruction fetch
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input logic pc_set_i, // pc was set to a new value
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input logic jump_i, // jump instruction seen (j, jr, jal, jalr)
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input logic branch_i, // branch instruction seen (bf, bnf)
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input logic branch_taken_i, // branch was taken
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input logic mem_load_i, // load from memory in this cycle
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input logic mem_store_i, // store to memory in this cycle
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input logic [N_EXT_CNT-1:0] ext_counters_i
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);
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localparam N_PERF_COUNTERS = 11 + N_EXT_CNT;
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`ifdef ASIC_SYNTHESIS
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localparam N_PERF_REGS = 1;
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`else
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localparam N_PERF_REGS = N_PERF_COUNTERS;
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`endif
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`define MSTATUS_UIE_BITS 0
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`define MSTATUS_SIE_BITS 1
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`define MSTATUS_MIE_BITS 3
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`define MSTATUS_UPIE_BITS 4
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`define MSTATUS_SPIE_BITS 5
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`define MSTATUS_MPIE_BITS 7
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`define MSTATUS_SPP_BITS 8
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`define MSTATUS_MPP_BITS 12:11
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typedef struct packed {
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//logic uie; - unimplemented, hardwired to '0
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// logic sie; - unimplemented, hardwired to '0
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// logic hie; - unimplemented, hardwired to '0
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logic mie;
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//logic upie; - unimplemented, hardwired to '0
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// logic spie; - unimplemented, hardwired to '0
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// logic hpie; - unimplemented, hardwired to '0
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logic mpie;
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// logic spp; - unimplemented, hardwired to '0
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// logic[1:0] hpp; - unimplemented, hardwired to '0
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PrivLvl_t mpp;
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} Status_t;
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// Performance Counter Signals
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logic id_valid_q;
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logic [N_PERF_COUNTERS-1:0] PCCR_in; // input signals for each counter category
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logic [N_PERF_COUNTERS-1:0] PCCR_inc, PCCR_inc_q; // should the counter be increased?
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logic [N_PERF_REGS-1:0] [31:0] PCCR_q, PCCR_n; // performance counters counter register
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logic [1:0] PCMR_n, PCMR_q; // mode register, controls saturation and global enable
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logic [N_PERF_COUNTERS-1:0] PCER_n, PCER_q; // selected counter input
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logic [31:0] perf_rdata;
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logic [4:0] pccr_index;
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logic pccr_all_sel;
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logic is_pccr;
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logic is_pcer;
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logic is_pcmr;
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// CSR update logic
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logic [31:0] csr_wdata_int;
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logic [31:0] csr_rdata_int;
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logic csr_we_int;
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// Interrupt control signals
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logic [31:0] mepc_q, mepc_n;
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logic [ 5:0] mcause_q, mcause_n;
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Status_t mstatus_q, mstatus_n;
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////////////////////////////////////////////
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// ____ ____ ____ ____ //
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// / ___/ ___|| _ \ | _ \ ___ __ _ //
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// | | \___ \| |_) | | |_) / _ \/ _` | //
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// | |___ ___) | _ < | _ < __/ (_| | //
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// \____|____/|_| \_\ |_| \_\___|\__, | //
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// |___/ //
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////////////////////////////////////////////
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// read logic
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always_comb
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begin
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csr_rdata_int = '0;
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case (csr_addr_i)
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// mstatus: always M-mode, contains IE bit
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12'h300: csr_rdata_int = {
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19'b0,
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mstatus_q.mpp,
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3'b0,
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mstatus_q.mpie,
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3'h0,
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mstatus_q.mie,
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3'h0
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};
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// mtvec: machine trap-handler base address
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12'h305: csr_rdata_int = {boot_addr_i, 8'h0};
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// mepc: exception program counter
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12'h341: csr_rdata_int = mepc_q;
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// mcause: exception cause
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12'h342: csr_rdata_int = {mcause_q[5], 26'b0, mcause_q[4:0]};
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// mhartid: unique hardware thread id
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12'hF14: csr_rdata_int = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};
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default: ;
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endcase
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end
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// write logic
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always_comb
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begin
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mepc_n = mepc_q;
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mstatus_n = mstatus_q;
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mcause_n = mcause_q;
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case (csr_addr_i)
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// mstatus: IE bit
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12'h300: if (csr_we_int) begin
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mstatus_n = '{
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mie: csr_wdata_int[`MSTATUS_MIE_BITS],
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mpie: csr_wdata_int[`MSTATUS_MPIE_BITS],
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mpp: PrivLvl_t'(PRIV_LVL_M)
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};
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end
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// mepc: exception program counter
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12'h341: if (csr_we_int) mepc_n = csr_wdata_int;
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// mcause
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12'h342: if (csr_we_int) mcause_n = {csr_wdata_int[31], csr_wdata_int[4:0]};
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default: ;
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endcase
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// exception controller gets priority over other writes
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unique case (1'b1)
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csr_save_cause_i: begin
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unique case (1'b1)
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csr_save_if_i:
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mepc_n = pc_if_i;
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csr_save_id_i:
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mepc_n = pc_id_i;
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default:;
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endcase
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mstatus_n.mpie = mstatus_q.mie;
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mstatus_n.mie = 1'b0;
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mcause_n = csr_cause_i;
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end //csr_save_cause_i
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csr_restore_mret_i: begin //MRET
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mstatus_n.mie = mstatus_q.mpie;
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mstatus_n.mpie = 1'b1;
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end //csr_restore_mret_i
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default:;
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endcase
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end
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// CSR operation logic
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always_comb
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begin
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csr_wdata_int = csr_wdata_i;
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csr_we_int = 1'b1;
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unique case (csr_op_i)
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CSR_OP_WRITE: csr_wdata_int = csr_wdata_i;
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CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o;
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CSR_OP_CLEAR: csr_wdata_int = (~csr_wdata_i) & csr_rdata_o;
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CSR_OP_NONE: begin
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csr_wdata_int = csr_wdata_i;
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csr_we_int = 1'b0;
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end
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default:;
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endcase
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end
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// output mux
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always_comb
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begin
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csr_rdata_o = csr_rdata_int;
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// performance counters
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if (is_pccr || is_pcer || is_pcmr)
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csr_rdata_o = perf_rdata;
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end
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// directly output some registers
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assign m_irq_enable_o = mstatus_q.mie;
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assign mepc_o = mepc_q;
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// actual registers
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0)
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begin
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mstatus_q <= '{
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mie: 1'b0,
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mpie: 1'b0,
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mpp: PRIV_LVL_M
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};
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mepc_q <= '0;
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mcause_q <= '0;
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end
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else
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begin
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// update CSRs
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mstatus_q <= '{
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mie: mstatus_n.mie,
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mpie: mstatus_n.mpie,
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mpp: PRIV_LVL_M
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};
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mepc_q <= mepc_n;
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mcause_q <= mcause_n;
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end
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end
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/////////////////////////////////////////////////////////////////
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// ____ __ ____ _ //
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// | _ \ ___ _ __ / _| / ___|___ _ _ _ __ | |_ ___ _ __ //
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// | |_) / _ \ '__| |_ | | / _ \| | | | '_ \| __/ _ \ '__| //
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// | __/ __/ | | _| | |__| (_) | |_| | | | | || __/ | //
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// |_| \___|_| |_|(_) \____\___/ \__,_|_| |_|\__\___|_| //
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// //
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/////////////////////////////////////////////////////////////////
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assign PCCR_in[0] = 1'b1; // cycle counter
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assign PCCR_in[1] = if_valid_i; // instruction counter
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assign PCCR_in[2] = 1'b0; // Reserved
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assign PCCR_in[3] = 1'b0; // Reserved
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assign PCCR_in[4] = imiss_i & (~pc_set_i); // cycles waiting for instruction fetches, excluding jumps and branches
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assign PCCR_in[5] = mem_load_i; // nr of loads
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assign PCCR_in[6] = mem_store_i; // nr of stores
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assign PCCR_in[7] = jump_i; // nr of jumps (unconditional)
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assign PCCR_in[8] = branch_i; // nr of branches (conditional)
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assign PCCR_in[9] = branch_taken_i; // nr of taken branches (conditional)
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assign PCCR_in[10] = id_valid_i & is_decoding_i & is_compressed_i; // compressed instruction counter
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// assign external performance counters
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generate
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genvar i;
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for (i = 0; i < N_EXT_CNT; i++)
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begin : g_extcounters
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assign PCCR_in[N_PERF_COUNTERS - N_EXT_CNT + i] = ext_counters_i[i];
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end
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endgenerate
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// address decoder for performance counter registers
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always_comb
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begin
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is_pccr = 1'b0;
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is_pcmr = 1'b0;
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is_pcer = 1'b0;
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pccr_all_sel = 1'b0;
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pccr_index = '0;
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perf_rdata = '0;
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// only perform csr access if we actually care about the read data
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if (csr_access_i) begin
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unique case (csr_addr_i)
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12'h7A0: begin
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is_pcer = 1'b1;
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perf_rdata[15:0] = PCER_q;
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end
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12'h7A1: begin
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is_pcmr = 1'b1;
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perf_rdata[1:0] = PCMR_q;
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end
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12'h79F: begin
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is_pccr = 1'b1;
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pccr_all_sel = 1'b1;
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end
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default:;
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endcase
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// look for 780 to 79F, Performance Counter Counter Registers
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if (csr_addr_i[11:5] == 7'b0111100) begin
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is_pccr = 1'b1;
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pccr_index = csr_addr_i[4:0];
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`ifdef ASIC_SYNTHESIS
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perf_rdata = PCCR_q[0];
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`else
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perf_rdata = csr_addr_i[4:0] < N_PERF_COUNTERS ? PCCR_q[csr_addr_i[4:0]] : '0;
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`endif
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end
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end
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end
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// performance counter counter update logic
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`ifdef ASIC_SYNTHESIS
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// for synthesis we just have one performance counter register
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assign PCCR_inc[0] = (|(PCCR_in & PCER_q)) & PCMR_q[0];
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always_comb
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begin
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PCCR_n[0] = PCCR_q[0];
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if ((PCCR_inc_q[0] == 1'b1) && ((PCCR_q[0] != 32'hFFFFFFFF) || (PCMR_q[1] == 1'b0)))
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PCCR_n[0] = PCCR_q[0] + 1;
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if (is_pccr == 1'b1) begin
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unique case (csr_op_i)
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CSR_OP_NONE: ;
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CSR_OP_WRITE: PCCR_n[0] = csr_wdata_i;
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CSR_OP_SET: PCCR_n[0] = csr_wdata_i | PCCR_q[0];
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CSR_OP_CLEAR: PCCR_n[0] = csr_wdata_i & ~(PCCR_q[0]);
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endcase
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end
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end
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`else
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always_comb
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begin
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for(int i = 0; i < N_PERF_COUNTERS; i++)
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begin : PERF_CNT_INC
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PCCR_inc[i] = PCCR_in[i] & PCER_q[i] & PCMR_q[0];
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PCCR_n[i] = PCCR_q[i];
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if ((PCCR_inc_q[i] == 1'b1) && ((PCCR_q[i] != 32'hFFFFFFFF) || (PCMR_q[1] == 1'b0)))
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PCCR_n[i] = PCCR_q[i] + 1;
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if (is_pccr == 1'b1 && (pccr_all_sel == 1'b1 || pccr_index == i)) begin
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unique case (csr_op_i)
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CSR_OP_NONE: ;
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CSR_OP_WRITE: PCCR_n[i] = csr_wdata_i;
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CSR_OP_SET: PCCR_n[i] = csr_wdata_i | PCCR_q[i];
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CSR_OP_CLEAR: PCCR_n[i] = csr_wdata_i & ~(PCCR_q[i]);
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endcase
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end
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end
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end
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`endif
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// update PCMR and PCER
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always_comb
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begin
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PCMR_n = PCMR_q;
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PCER_n = PCER_q;
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if (is_pcmr) begin
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unique case (csr_op_i)
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CSR_OP_NONE: ;
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CSR_OP_WRITE: PCMR_n = csr_wdata_i[1:0];
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CSR_OP_SET: PCMR_n = csr_wdata_i[1:0] | PCMR_q;
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CSR_OP_CLEAR: PCMR_n = csr_wdata_i[1:0] & ~(PCMR_q);
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endcase
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end
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if (is_pcer) begin
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unique case (csr_op_i)
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CSR_OP_NONE: ;
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CSR_OP_WRITE: PCER_n = csr_wdata_i[N_PERF_COUNTERS-1:0];
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CSR_OP_SET: PCER_n = csr_wdata_i[N_PERF_COUNTERS-1:0] | PCER_q;
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CSR_OP_CLEAR: PCER_n = csr_wdata_i[N_PERF_COUNTERS-1:0] & ~(PCER_q);
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endcase
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end
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end
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// Performance Counter Registers
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0)
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begin
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id_valid_q <= 1'b0;
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PCER_q <= '0;
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PCMR_q <= 2'h3;
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for(int i = 0; i < N_PERF_REGS; i++)
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begin
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PCCR_q[i] <= '0;
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PCCR_inc_q[i] <= '0;
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end
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end
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else
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begin
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id_valid_q <= id_valid_i;
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PCER_q <= PCER_n;
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PCMR_q <= PCMR_n;
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for(int i = 0; i < N_PERF_REGS; i++)
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begin
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PCCR_q[i] <= PCCR_n[i];
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PCCR_inc_q[i] <= PCCR_inc[i];
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end
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end
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end
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endmodule
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