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27e68bd76e
This change has been informed by advice from the lowRISC legal committee. The Solderpad 0.51 license states "the Licensor permits any Work licensed under this License, at the option of the Licensee, to be treated as licensed under the Apache License Version 2.0". We use this freedom to convert license markings to Apache 2.0. This commit ensures that we retain all authorship and copyright attribution information.
103 lines
3.1 KiB
Systemverilog
103 lines
3.1 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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////////////////////////////////////////////////////////////////////////////////
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// Engineer: Davide Schiavone - pschiavo@iis.ee.ethz.ch //
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// //
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// Additional contributions by: //
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// //
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// Design Name: Interrupt Controller //
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// Project Name: ibex //
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// Language: SystemVerilog //
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// //
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// Description: Interrupt Controller of the pipelined processor //
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// //
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////////////////////////////////////////////////////////////////////////////////
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import ibex_defines::*;
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module ibex_int_controller
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(
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input logic clk,
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input logic rst_n,
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// irq_req for controller
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output logic irq_req_ctrl_o,
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output logic [4:0] irq_id_ctrl_o,
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// handshake signals to controller
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input logic ctrl_ack_i,
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input logic ctrl_kill_i,
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// external interrupt lines
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input logic irq_i, // level-triggered interrupt inputs
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input logic [4:0] irq_id_i, // interrupt id [0,1,....31]
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input logic m_IE_i // interrupt enable bit from CSR (M mode)
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);
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enum logic [1:0] { IDLE, IRQ_PENDING, IRQ_DONE} exc_ctrl_cs;
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logic irq_enable_ext;
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logic [4:0] irq_id_q;
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assign irq_enable_ext = m_IE_i;
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assign irq_req_ctrl_o = exc_ctrl_cs == IRQ_PENDING;
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assign irq_id_ctrl_o = irq_id_q;
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0) begin
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irq_id_q <= '0;
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exc_ctrl_cs <= IDLE;
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end else begin
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unique case (exc_ctrl_cs)
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IDLE:
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begin
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if(irq_enable_ext & irq_i) begin
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exc_ctrl_cs <= IRQ_PENDING;
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irq_id_q <= irq_id_i;
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end
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end
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IRQ_PENDING:
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begin
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unique case(1'b1)
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ctrl_ack_i:
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exc_ctrl_cs <= IRQ_DONE;
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ctrl_kill_i:
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exc_ctrl_cs <= IDLE;
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default:
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exc_ctrl_cs <= IRQ_PENDING;
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endcase
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end
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IRQ_DONE:
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begin
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exc_ctrl_cs <= IDLE;
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end
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endcase
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end
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end
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`ifndef SYNTHESIS
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// synopsys translate_off
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// evaluate at falling edge to avoid duplicates during glitches
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// Removed this message as it pollutes too much the output and makes tests fail
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//always_ff @(negedge clk)
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//begin
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// if (rst_n && exc_ctrl_cs == IRQ_DONE)
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// $display("%t: Entering interrupt service routine. [%m]", $time);
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//end
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// synopsys translate_on
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`endif
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endmodule
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