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This change has been informed by advice from the lowRISC legal committee. The Solderpad 0.51 license states "the Licensor permits any Work licensed under this License, at the option of the Licensee, to be treated as licensed under the Apache License Version 2.0". We use this freedom to convert license markings to Apache 2.0. This commit ensures that we retain all authorship and copyright attribution information.
98 lines
3 KiB
Systemverilog
98 lines
3 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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////////////////////////////////////////////////////////////////////////////////
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// Engineer: Francesco Conti - f.conti@unibo.it //
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// //
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// Additional contributions by: //
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// Markus Wegmann - markus.wegmann@technokrat.ch //
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// //
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// Design Name: RISC-V register file //
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// Project Name: ibex //
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// Language: SystemVerilog //
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// //
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// Description: Register file with 31 or 15x 32 bit wide registers. //
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// Register 0 is fixed to 0. This register file is based on //
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// flip flops. //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "ibex_config.sv"
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module ibex_register_file
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#(
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parameter RV32E = 0,
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parameter DATA_WIDTH = 32
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)
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(
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// Clock and Reset
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input logic clk,
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input logic rst_n,
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input logic test_en_i,
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//Read port R1
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input logic [4:0] raddr_a_i,
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output logic [DATA_WIDTH-1:0] rdata_a_o,
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//Read port R2
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input logic [4:0] raddr_b_i,
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output logic [DATA_WIDTH-1:0] rdata_b_o,
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// Write port W1
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input logic [4:0] waddr_a_i,
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input logic [DATA_WIDTH-1:0] wdata_a_i,
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input logic we_a_i
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);
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localparam ADDR_WIDTH = RV32E ? 4 : 5;
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localparam NUM_WORDS = 2**ADDR_WIDTH;
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logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] rf_reg;
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logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] rf_reg_tmp;
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logic [NUM_WORDS-1:0] we_a_dec;
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always_comb
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begin : we_a_decoder
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for (int i = 0; i < NUM_WORDS; i++) begin
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if (waddr_a_i == i)
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we_a_dec[i] = we_a_i;
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else
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we_a_dec[i] = 1'b0;
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end
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end
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genvar i;
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generate
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// loop from 1 to NUM_WORDS-1 as R0 is nil
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for (i = 1; i < NUM_WORDS; i++)
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begin : rf_gen
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always_ff @(posedge clk, negedge rst_n)
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begin : register_write_behavioral
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if (rst_n==1'b0) begin
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rf_reg_tmp[i] <= 'b0;
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end else begin
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if (we_a_dec[i])
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rf_reg_tmp[i] <= wdata_a_i;
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end
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end
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end
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// R0 is nil
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assign rf_reg[0] = '0;
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assign rf_reg[NUM_WORDS-1:1] = rf_reg_tmp[NUM_WORDS-1:1];
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endgenerate
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assign rdata_a_o = rf_reg[raddr_a_i];
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assign rdata_b_o = rf_reg[raddr_b_i];
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endmodule
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