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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
3a42f12e64
This commit was prepared by the following script, followed by manual
fixes as needed.
```sh
sed -e 's/zeroriscy/ibex/g' -i.bak *.sv *.md *.yml
sed -e 's/zero-riscy/ibex/g' -i.bak *.sv *.md *.yml
sed -e 's/zeroriscy/ibex/g' -i.bak include/*.sv
sed -e 's/zero-riscy/ibex/g' -i.bak include/*.sv
sed -e 's/cluster_clock_gating/clock_gating/g' -i.bak *.sv
rm -f *.bak
rm -f include/*.bak
find . -name 'zeroriscy_*' -exec bash -c 'file={}; git mv $file ${file/zeroriscy/ibex}' \;
```
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|---|---|---|
| ci | ||
| doc | ||
| include | ||
| .gitignore | ||
| .gitlab-ci.yml | ||
| ibex_alu.sv | ||
| ibex_compressed_decoder.sv | ||
| ibex_controller.sv | ||
| ibex_core.sv | ||
| ibex_cs_registers.sv | ||
| ibex_debug_unit.sv | ||
| ibex_decoder.sv | ||
| ibex_ex_block.sv | ||
| ibex_fetch_fifo.sv | ||
| ibex_id_stage.sv | ||
| ibex_if_stage.sv | ||
| ibex_int_controller.sv | ||
| ibex_load_store_unit.sv | ||
| ibex_multdiv_fast.sv | ||
| ibex_multdiv_slow.sv | ||
| ibex_prefetch_buffer.sv | ||
| ibex_register_file.sv | ||
| ibex_register_file_ff.sv | ||
| ibex_tracer.sv | ||
| LICENSE | ||
| README.md | ||
| src_files.yml | ||
ibex: RISC-V Core
ibex is a small 2-stage RISC-V core derived from RI5CY.
ibex fully implements the RV32IMC instruction set and a minimal set of RISCV privileged specifications. ibex can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions. This configuration is called micro-riscy
The core was developed as part of the PULP platform for energy-efficient computing and is currently used as the control core for PULP and PULPino.
Documentation
A datasheet that explains the most important features of the core can be found in the doc folder.