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Greg Chadwick 639964514c [RTL] Added seperate ALU for branch target 
On branches now compute target same cycle as the condition.  This
removes a stall cycle from all taken conditional branches.
2020-01-31 09:32:20 +00:00
..
fpga/artya7 FPGA example: add support for the Arty A7-35 2020-01-27 20:18:17 +00:00
simple_system [RTL] Added seperate ALU for branch target 2020-01-31 09:32:20 +00:00
sw sw-led: do not hardcode CC in makefile 2020-01-27 20:18:17 +00:00