ibex/rtl
Bert Pieters fdfdcc0467 [rtl] disable clock between reset and fetch_enable_i
Fixes lowRISC#957

Signed-off-by: Bert Pieters <bert.pieters@gmail.com>
2020-06-22 13:25:39 +02:00
..
ibex_alu.sv [bitmanip] Add ZBR instruction group 2020-05-22 17:21:03 +02:00
ibex_compressed_decoder.sv [rtl] Introduce default clk/reset to prim_assert 2020-02-10 09:42:52 +00:00
ibex_controller.sv [rtl] disable clock between reset and fetch_enable_i 2020-06-22 13:25:39 +02:00
ibex_core.f Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr 2020-03-06 12:49:51 +01:00
ibex_core.sv [rtl] disable clock between reset and fetch_enable_i 2020-06-22 13:25:39 +02:00
ibex_core_tracing.sv [rtl] Add RVFI IXL interface 2020-05-25 16:47:25 +01:00
ibex_counter.sv [rtl] Rewrite perf counters to be Yosys compatible 2020-06-08 11:20:09 +01:00
ibex_cs_registers.sv [rtl] Rewrite perf counters to be Yosys compatible 2020-06-08 11:20:09 +01:00
ibex_decoder.sv [rtl] Remove use of `define in decoder 2020-06-18 15:38:05 +01:00
ibex_dummy_instr.sv [rtl] Add dummy instruction insertion 2020-05-21 13:58:01 +01:00
ibex_ex_block.sv [rtl] Add data-independent timing to multdiv_fast 2020-05-15 10:19:55 +01:00
ibex_fetch_fifo.sv [rtl] prefetch buffer performance fix 2020-06-01 08:59:51 +01:00
ibex_icache.sv Add some basic protocol checking to the icache's RAM interface 2020-06-22 10:37:34 +01:00
ibex_id_stage.sv [rtl] disable clock between reset and fetch_enable_i 2020-06-22 13:25:39 +02:00
ibex_if_stage.sv [rtl] Add speculative branch signal 2020-05-26 09:41:37 +01:00
ibex_load_store_unit.sv [rtl] Fix writeback stage interrupt issue 2020-06-10 15:13:32 +01:00
ibex_multdiv_fast.sv [rtl] Add data-independent timing to multdiv_fast 2020-05-15 10:19:55 +01:00
ibex_multdiv_slow.sv [rtl] data-independent execution for multdiv_slow 2020-05-15 10:19:55 +01:00
ibex_pkg.sv [rtl] Add RVFI IXL interface 2020-05-25 16:47:25 +01:00
ibex_pmp.sv [rtl] Fix PMP NA4 address matching 2020-06-02 13:41:03 +01:00
ibex_prefetch_buffer.sv [rtl] prefetch buffer performance fix 2020-06-01 08:59:51 +01:00
ibex_register_file_ff.sv [rtl] Use generate loop in FF register file 2020-06-12 10:31:54 +01:00
ibex_register_file_fpga.sv [rtl] Add dummy instruction insertion 2020-05-21 13:58:01 +01:00
ibex_register_file_latch.sv [rtl] Use outer generate loop for latch RF 2020-06-12 12:05:48 +01:00
ibex_tracer.sv [rtl] Add RVFI IXL interface 2020-05-25 16:47:25 +01:00
ibex_tracer_pkg.sv [bitmanip] Add ZBR instruction group 2020-05-22 17:21:03 +02:00
ibex_wb_stage.sv [rtl] Fix writeback stage interrupt issue 2020-06-10 15:13:32 +01:00