Tom Roberts 1a9545baaf [rtl] Add CSR module and instantiate ... - This change should have no functional impact on the design - Adding the separate module will allow easy parameterization of security hardening for individual CSRs in the future - As a side benefit, clock gating is added for CSRs that didn't previously have it - Note that this change makes the cpuctrl register always present, rather than individual bits being added depending on parameterized features. This is not ideal, but the parameterization becomes rather messy otherwise. Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>		2020-10-14 15:53:33 +01:00
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verible_waiver.vbw	Add RegFile parameter for selecting register file implementation	2020-08-21 14:20:34 +02:00
verilator_waiver.vlt	[rtl] Add CSR module and instantiate	2020-10-14 15:53:33 +01:00