Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucorehardwarerisc-vrv32

Sven Stucki 60a842c81d Added all RiscV CSR manipulation instructions, major update and cleanup		2015-06-01 01:01:33 +02:00
include	Added all RiscV CSR manipulation instructions, major update and cleanup	2015-06-01 01:01:33 +02:00
alu.sv	Realigned RiscV with Or10n, code cleanup	2015-05-24 23:04:36 +02:00
controller.sv	Added all RiscV CSR manipulation instructions, major update and cleanup	2015-06-01 01:01:33 +02:00
cs_registers.sv	Added all RiscV CSR manipulation instructions, major update and cleanup	2015-06-01 01:01:33 +02:00
debug_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
ex_stage.sv	Added all RiscV CSR manipulation instructions, major update and cleanup	2015-06-01 01:01:33 +02:00
exc_controller.sv	RiscV: exception controller and CSR core and synthesis update	2015-05-26 00:08:44 +02:00
id_stage.sv	Added all RiscV CSR manipulation instructions, major update and cleanup	2015-06-01 01:01:33 +02:00
if_stage.sv	RiscV: exception controller and CSR core and synthesis update	2015-05-26 00:08:44 +02:00
instr_core_interface.sv	Fixed space/tab mixture and indentation in instr_core_interface	2015-04-16 15:21:03 +02:00
load_store_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
mult.sv	Realigned RiscV with Or10n, code cleanup	2015-05-24 23:04:36 +02:00
register_file.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
riscv_core.sv	Added all RiscV CSR manipulation instructions, major update and cleanup	2015-06-01 01:01:33 +02:00
wb_stage.sv	Added all RiscV CSR manipulation instructions, major update and cleanup	2015-06-01 01:01:33 +02:00