ibex/examples
Canberk Topal 9af580f6d9 [fpga] Add power analysis scripts to FPGA example
This commit adds power analysis scripts to the Arty A7
example design. They can be used by setting the newly
added `FPGAPowerAnalysis` parameter to 1.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2021-08-03 16:51:16 +01:00
..
fpga/artya7 [fpga] Add power analysis scripts to FPGA example 2021-08-03 16:51:16 +01:00
simple_system [rtl] Wire scan_rst_ni through ibex_top_tracing 2021-04-21 12:41:24 +01:00
sw [sw/fpga] coremark/link.ld update for FPGA sim 2021-08-03 16:51:16 +01:00