75dadb5aef
As a result of lowRISC/opentitan#2405 and lowRISC/ibex#928 (reporting that interrupts that came in while a load instruction was in the ID stage caused some incorrect behavior in Ibex), this PR adds some new directed interrupt and debug tests to check that the core behaves properly during execution of each supported instruction when some external irq/debug stimulus comes in. To do this, we use the two new functions `decode_instr(...)` and `decode_compressed_instr(...)` in `core_ibex_test_list.sv` to "decode" every instruction that the `core_ibex_instr_monitor_if` sees in the ID stage of the pipeline. Once the testbench decodes an instruction that we have not seen before, it can then drive interrupt or debug stimulus into the core. Once any given instruction has been detected by the testbench (and stimulus driven), it will no longer drive stimulus if this instruction is seen in the decode pipeline (e.g. if we have previously detected a `c.addi` instruction in the ID stage and have driven irq/debug stimulus, we will no longer drive stimulus if we see another `c.addi` instruction, no matter the operands). This is to avoid driving irq/debug stimulus after every single instruction as this will add a huge unwanted amount of simulation latency. A few notes: - We drive irq/debug stimulus into the core every time we see a `wfi` instruction, as otherwise we will timeout as the core waits infinitely for some stimulus from the outside world. - We ignore some system-level instructions (ebreak/mret/dret) and illegal instructionsfor now, as driving stimulus during these instructions will result in a nested trap, which requires special handling. - The interrupt agent was modified slightly to drive stimulus by default on the falling edge of the clock, so this way we can "catch" instructions that are in the ID pipeline for only a single cycle. - The duration for which the testbench raises `debug_req_i` for the core is also increased to avoid edge cases where we lower the debug line too early (e.g. while long multicycle instructions like `div` are executing in the ID stage). |
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| ci | ||
| doc | ||
| dv | ||
| examples | ||
| formal | ||
| lint | ||
| rtl | ||
| shared | ||
| syn | ||
| util | ||
| vendor | ||
| .clang-format | ||
| .gitignore | ||
| azure-pipelines.yml | ||
| check_tool_requirements.core | ||
| CONTRIBUTING.md | ||
| CREDITS.md | ||
| ibex_configs.yaml | ||
| ibex_core.core | ||
| ibex_core_tracing.core | ||
| ibex_icache.core | ||
| ibex_pkg.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| Makefile | ||
| python-requirements.txt | ||
| README.md | ||
| src_files.yml | ||
| tool_requirements.py | ||
Ibex RISC-V Core
Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.
This core was initially developed as part of the PULP platform under the name "Zero-riscy" [1], and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.
Configuration
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features. The table below indicates performance, area and verification status for a few selected configurations. These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).
| Config | "small" | "maxperf" | "maxperf-pmp-bmfull" |
|---|---|---|---|
| Features | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (CoreMark/MHz) | 2.44 | 3.09 | 3.09 |
| Area - Yosys (kGE) | 33.15 | 39.03 | 63.32 |
| Area - Commercial (estimated kGE) | ~27 | ~31 | ~50 |
| Verification status | Green | Amber | Amber |
Notes:
- Performance numbers are based on CoreMark running on the Ibex Simple System platform. Note that CoreMark was compiled without support for the B extension.
- Yosys synthesis area numbers are based on the Ibex basic synthesis flow.
- Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
- Verification status is a rough guide to the overall maturity of a particular configuration. Green indicates that verification is close to complete. Amber indicates that some verification has been performed, but the configuration is still experimental. Red indicates a new configuration with minimal/no verification. Users must make their own assessment of verification readiness for any tapeout.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style
guide.
All C and C++ code should be formatted with clang-format before committing.
Either run clang-format -i filename.cc or git clang-format on added files.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Credits
Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.