mirror of
https://github.com/lowRISC/ibex.git
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f9ad280d0c
- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include' directory, since these files are not actually included. - Remove ibex_config.sv, it's mostly unused code. The remaining defines, SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should be set through command-line flags to the simulation/synthesis tools. Initial version by Nils Gräf.
36 lines
1.1 KiB
Text
36 lines
1.1 KiB
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex:0.1"
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description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr ISA"
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filesets:
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files_rtl:
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files:
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- rtl/ibex_defines.sv
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- rtl/ibex_tracer_defines.sv
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- rtl/ibex_alu.sv
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- rtl/ibex_compressed_decoder.sv
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- rtl/ibex_controller.sv
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- rtl/ibex_cs_registers.sv
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- rtl/ibex_decoder.sv
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- rtl/ibex_ex_block.sv
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- rtl/ibex_fetch_fifo.sv
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- rtl/ibex_id_stage.sv
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- rtl/ibex_if_stage.sv
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- rtl/ibex_int_controller.sv
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- rtl/ibex_load_store_unit.sv
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- rtl/ibex_multdiv_fast.sv
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- rtl/ibex_multdiv_slow.sv
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- rtl/ibex_prefetch_buffer.sv
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# XXX: Figure out the best way to switch these two implementations
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# dynamically on the target.
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# - rtl/ibex_register_file.sv # ASIC
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- rtl/ibex_register_file_ff.sv # FPGA
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- rtl/ibex_core.sv
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file_type: systemVerilogSource
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targets:
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default:
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filesets:
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- files_rtl
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