Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Find a file
Alex Bradbury 7e81f6f4eb Standardise "subheadings" in code comments
The code base made extensive use of ASCII art headings/subheadings in
comments to delineate code. Switch to a more space efficient and easier
to edit format:

/////////
// Foo //
/////////
2019-04-26 15:09:00 +01:00
doc Add a bit of history to the documentation 2019-04-26 15:09:00 +01:00
rtl Standardise "subheadings" in code comments 2019-04-26 15:09:00 +01:00
.gitignore Fix some issues and cleanup 2016-12-30 00:26:15 +01:00
ibex.core Switch to execution-based debug 2019-04-26 15:09:00 +01:00
ibex_tracer.core Add initial fusesoc support 2019-04-26 15:09:00 +01:00
LICENSE Convert from Solderpad to standard Apache 2.0 license 2019-04-26 15:05:17 +01:00
README.md Update README 2019-04-26 15:09:00 +01:00
src_files.yml Rename zeroriscy to ibex 2019-04-26 15:05:01 +01:00

Ibex: RISC-V Core

Ibex is a small 32 bit RISC-V core with a 2-stage pipeline.

Ibex fully implements the RV32IMC instruction set and a small set of RISC-V privileged specifications. Ibex can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions.

This core was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further.

Ibex is under active development, with further code cleanups, feature additions, and test and verification planned for the future.

Documentation

A datasheet that explains the most important features of the core can be found in the doc folder.

License

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).