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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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Pasquale Davide Schiavone bd96611340 merge with new controller
2017-02-28 16:34:39 +01:00
include update ready controller 2017-02-28 11:40:00 +01:00
tb/serDiv Compile all files 2017-01-12 19:34:41 +01:00
.gitignore Fix some issues and cleanup 2016-12-30 00:26:15 +01:00
alu.sv added multipliers 2017-02-28 12:48:13 +01:00
compressed_decoder.sv General updates and renaming 2017-02-16 19:07:17 +01:00
controller.sv Fixed debug and changed controller 2017-02-28 16:23:58 +01:00
cs_registers.sv Fixed debug and changed controller 2017-02-28 16:23:58 +01:00
debug_unit.sv Fixed debug and changed controller 2017-02-28 16:23:58 +01:00
decoder.sv merge with new controller 2017-02-28 16:34:39 +01:00
ex_stage.sv added multipliers 2017-02-28 12:48:13 +01:00
exc_controller.sv General updates and renaming 2017-02-16 19:07:17 +01:00
id_stage.sv merge with new controller 2017-02-28 16:34:39 +01:00
if_stage.sv Fixed debug and changed controller 2017-02-28 16:23:58 +01:00
LICENSE Added LICENSE file and started adding headers 2015-12-11 17:20:07 +01:00
load_store_unit.sv update ready controller 2017-02-28 11:40:00 +01:00
prefetch_buffer.sv Updated 2017-02-17 10:02:26 +01:00
prefetch_L0_buffer.sv Updated 2017-02-17 10:02:26 +01:00
README.md Updated 2017-02-17 10:02:26 +01:00
register_file.sv Updated 2017-02-17 10:02:26 +01:00
register_file_ff.sv Updated 2017-02-17 10:02:26 +01:00
riscv_simchecker.sv Updated 2017-02-17 10:02:26 +01:00
riscv_tracer.sv General updates and renaming 2017-02-16 19:07:17 +01:00
src_files.yml added multipliers 2017-02-28 12:48:13 +01:00
zeroriscy_core.sv merge with new controller 2017-02-28 16:34:39 +01:00
zeroriscy_tracer.sv Updated 2017-02-17 10:02:26 +01:00

README.md

zero-riscy: RISC-V Core

zero-riscy is a small 3-stage RISC-V core derivated by littleRISCV.

zero-riscy fully implements the RV32IC instruction set and it is meant for control code.