c15f3b8888
This is triggered by the fact that if the ICache parameter is false then we don't instantiate the ibex_icache module. For verilator simulations, the module is then discarded entirely, which means that its two DPI functions are not defined. That's unfortunate because we're also compiling the code in scrambled_ecc32_mem_area.cc, which expects the functions to be defined. The obvious solution (don't include scrambled_ecc32_mem_area.cc if you don't have an icache) isn't easy to do, because FuseSoc doesn't currently allow us to use parameters to configure its dependency tree (see fusesoc issue 438 for a discussion). The super-clever solution that I came up with before(!) was to declare these symbols as weak in the C++ code. That way, we can do a runtime check to make sure that no-one is silly enough to call them without an icache, but everything will still build properly either way. Unfortunately, that doesn't work well with xcelium simulations. Xcelium turns out to compile all the C++ code into one .so library and generate functions for exported DPI functions in another. These two solibs then get loaded at runtime with dlopen(). But this doesn't work with weak symbols: in fact, it seems you end up with the C++ version every time. Boo! So let's be stupider about it and define (bogus) versions of the DPI functions in this case. Fortunately, both of them are designed to return zero on failure so we can just return zero and needn't worry too much. The idea is that when this lands, we can revert the OpenTitan change that switched the C++ code to using weak symbols and Xcelium simulations will start working. |
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| doc | ||
| dv | ||
| examples | ||
| formal | ||
| lint | ||
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| util | ||
| vendor | ||
| .clang-format | ||
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| .svlint.toml | ||
| azure-pipelines.yml | ||
| check_tool_requirements.core | ||
| CONTRIBUTING.md | ||
| CREDITS.md | ||
| ibex_configs.yaml | ||
| ibex_core.core | ||
| ibex_icache.core | ||
| ibex_multdiv.core | ||
| ibex_pkg.core | ||
| ibex_top.core | ||
| ibex_top_tracing.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| Makefile | ||
| python-requirements.txt | ||
| README.md | ||
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| tool_requirements.py | ||
Ibex RISC-V Core
Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.
The block diagram below shows the small parametrization with a 2-stage pipeline.
Ibex was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further. It is under active development.
Configuration
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features. The table below indicates performance, area and verification status for a few selected configurations. These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).
| Config | "micro" | "small" | "maxperf" | "maxperf-pmp-bmfull" |
|---|---|---|---|---|
| Features | RV32EC | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (CoreMark/MHz) | 0.904 | 2.47 | 3.13 | 3.13 |
| Area - Yosys (kGE) | 16.85 | 26.60 | 32.48 | 66.02 |
| Area - Commercial (estimated kGE) | ~15 | ~24 | ~30 | ~61 |
| Verification status | Red | Green | Amber | Amber |
Notes:
- Performance numbers are based on CoreMark running on the Ibex Simple System platform. Note that different ISAs (use of B and C extensions) give the best results for different configurations. See the Benchmarks README for more information.
- Yosys synthesis area numbers are based on the Ibex basic synthesis flow using the latch-based register file.
- Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
- For comparison, the original "Zero-riscy" core yields an area of 23.14kGE using our Yosys synthesis flow.
- Verification status is a rough guide to the overall maturity of a particular configuration. Green indicates that verification is close to complete. Amber indicates that some verification has been performed, but the configuration is still experimental. Red indicates a configuration with minimal/no verification. Users must make their own assessment of verification readiness for any tapeout.
- v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec. The latter are not ratified and there may be changes before ratification. See Standards Compliance in the Ibex documentation for more information.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style
guide.
All C and C++ code should be formatted with clang-format before committing.
Either run clang-format -i filename.cc or git clang-format on added files.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Credits
Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.