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232 lines
No EOL
7.9 KiB
Systemverilog
232 lines
No EOL
7.9 KiB
Systemverilog
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017 ETH Zurich, University of Bologna //
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// All rights reserved. //
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// //
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// This code is under development and not yet released to the public. //
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// Until it is released, the code is under the copyright of ETH Zurich //
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// and the University of Bologna, and may contain unpublished work. //
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// Any reuse/redistribution should only be under explicit permission. //
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// //
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// Bug fixes and contributions will eventually be released under the //
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// SolderPad open hardware license and under the copyright of ETH Zurich //
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// and the University of Bologna. //
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// //
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// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch //
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// //
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// Design Name: Fetch Fifo for 32 bit memory interface //
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// Project Name: zero-riscy //
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// Language: SystemVerilog //
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// //
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// Description: Fetch fifo //
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////////////////////////////////////////////////////////////////////////////////
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`include "zeroriscy_config.sv"
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// input port: send address one cycle before the data
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// clear_i clears the FIFO for the following cycle. in_addr_i can be sent in
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// this cycle already
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module zeroriscy_fetch_fifo
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(
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input logic clk,
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input logic rst_n,
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// control signals
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input logic clear_i, // clears the contents of the fifo
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// input port
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input logic [31:0] in_addr_i,
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input logic [31:0] in_rdata_i,
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input logic in_valid_i,
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output logic in_ready_o,
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// output port
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output logic out_valid_o,
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input logic out_ready_i,
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output logic [31:0] out_rdata_o,
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output logic [31:0] out_addr_o,
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output logic out_valid_stored_o // same as out_valid_o, except that if something is incoming now it is not included. This signal is available immediately as it comes directly out of FFs
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);
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localparam DEPTH = 3; // must be 3 or greater
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// index 0 is used for output
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logic [0:DEPTH-1] [31:0] addr_n, addr_int, addr_Q;
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logic [0:DEPTH-1] [31:0] rdata_n, rdata_int, rdata_Q;
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logic [0:DEPTH-1] valid_n, valid_int, valid_Q;
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logic [31:0] addr_next;
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logic [31:0] rdata, rdata_unaligned;
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logic valid, valid_unaligned;
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logic aligned_is_compressed, unaligned_is_compressed;
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logic aligned_is_compressed_st, unaligned_is_compressed_st;
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//////////////////////////////////////////////////////////////////////////////
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// output port
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//////////////////////////////////////////////////////////////////////////////
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assign rdata = (valid_Q[0]) ? rdata_Q[0] : in_rdata_i;
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assign valid = valid_Q[0] || in_valid_i;
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assign rdata_unaligned = (valid_Q[1]) ? {rdata_Q[1][15:0], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]};
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// it is implied that rdata_valid_Q[0] is set
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assign valid_unaligned = (valid_Q[1] || (valid_Q[0] && in_valid_i));
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assign unaligned_is_compressed = rdata[17:16] != 2'b11;
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assign aligned_is_compressed = rdata[1:0] != 2'b11;
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assign unaligned_is_compressed_st = rdata_Q[0][17:16] != 2'b11;
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assign aligned_is_compressed_st = rdata_Q[0][1:0] != 2'b11;
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//////////////////////////////////////////////////////////////////////////////
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// instruction aligner (if unaligned)
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//////////////////////////////////////////////////////////////////////////////
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always_comb
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begin
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// serve the aligned case even though the output address is unaligned when
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// the next instruction will be from a hardware loop target
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// in this case the current instruction is already prealigned in element 0
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if (out_addr_o[1]) begin
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// unaligned case
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out_rdata_o = rdata_unaligned;
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if (unaligned_is_compressed)
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out_valid_o = valid;
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else
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out_valid_o = valid_unaligned;
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end else begin
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// aligned case
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out_rdata_o = rdata;
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out_valid_o = valid;
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end
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end
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assign out_addr_o = (valid_Q[0]) ? addr_Q[0] : in_addr_i;
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// this valid signal must not depend on signals from outside!
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always_comb
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begin
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out_valid_stored_o = 1'b1;
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if (out_addr_o[1]) begin
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if (unaligned_is_compressed_st)
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out_valid_stored_o = 1'b1;
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else
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out_valid_stored_o = valid_Q[1];
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end else begin
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out_valid_stored_o = valid_Q[0];
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end
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end
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//////////////////////////////////////////////////////////////////////////////
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// input port
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//////////////////////////////////////////////////////////////////////////////
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// we accept data as long as our fifo is not full
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// we don't care about clear here as the data will be received one cycle
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// later anyway
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assign in_ready_o = ~valid_Q[DEPTH-2];
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//////////////////////////////////////////////////////////////////////////////
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// FIFO management
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//////////////////////////////////////////////////////////////////////////////
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always_comb
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begin
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int j;
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addr_int = addr_Q;
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rdata_int = rdata_Q;
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valid_int = valid_Q;
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if (in_valid_i) begin
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for(j = 0; j < DEPTH; j++) begin
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if (~valid_Q[j]) begin
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addr_int[j] = in_addr_i;
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rdata_int[j] = in_rdata_i;
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valid_int[j] = 1'b1;
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break;
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end
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end
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end
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end
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assign addr_next = {addr_int[0][31:2], 2'b00} + 32'h4;
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// move everything by one step
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always_comb
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begin
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addr_n = addr_int;
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rdata_n = rdata_int;
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valid_n = valid_int;
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if (out_ready_i && out_valid_o) begin
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begin
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if (addr_int[0][1]) begin
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// unaligned case
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if (unaligned_is_compressed) begin
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addr_n[0] = {addr_next[31:2], 2'b00};
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end else begin
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addr_n[0] = {addr_next[31:2], 2'b10};
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end
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rdata_n = {rdata_int[1:DEPTH-1], 32'b0};
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valid_n = {valid_int[1:DEPTH-1], 1'b0};
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end else begin
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if (aligned_is_compressed) begin
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// just increase address, do not move to next entry in FIFO
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addr_n[0] = {addr_int[0][31:2], 2'b10};
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end else begin
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// move to next entry in FIFO
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addr_n[0] = {addr_next[31:2], 2'b00};
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rdata_n = {rdata_int[1:DEPTH-1], 32'b0};
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valid_n = {valid_int[1:DEPTH-1], 1'b0};
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end
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end
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end
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end
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end
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//////////////////////////////////////////////////////////////////////////////
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// registers
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//////////////////////////////////////////////////////////////////////////////
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always_ff @(posedge clk, negedge rst_n)
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begin
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if(rst_n == 1'b0)
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begin
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addr_Q <= '{default: '0};
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rdata_Q <= '{default: '0};
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valid_Q <= '0;
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end
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else
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begin
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// on a clear signal from outside we invalidate the content of the FIFO
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// completely and start from an empty state
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if (clear_i) begin
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valid_Q <= '0;
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end else begin
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addr_Q <= addr_n;
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rdata_Q <= rdata_n;
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valid_Q <= valid_n;
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end
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end
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end
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//----------------------------------------------------------------------------
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// Assertions
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//----------------------------------------------------------------------------
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`ifndef VERILATOR
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assert property (
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@(posedge clk) (in_valid_i) |-> ((valid_Q[DEPTH-1] == 1'b0) || (clear_i == 1'b1)) );
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`endif
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endmodule |