Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Find a file
Philipp Wagner cec232b36d Set dcsr.priv to M-mode on reset
Port of RI5CY commit 7f4a446f95f02f5ce517c0abe32b4095eb10c0de
2019-04-26 15:09:00 +01:00
doc Convert from Solderpad to standard Apache 2.0 license 2019-04-26 15:05:17 +01:00
rtl Set dcsr.priv to M-mode on reset 2019-04-26 15:09:00 +01:00
.gitignore Fix some issues and cleanup 2016-12-30 00:26:15 +01:00
ibex.core Switch to execution-based debug 2019-04-26 15:09:00 +01:00
ibex_tracer.core Add initial fusesoc support 2019-04-26 15:09:00 +01:00
LICENSE Convert from Solderpad to standard Apache 2.0 license 2019-04-26 15:05:17 +01:00
README.md Rename zeroriscy to ibex 2019-04-26 15:05:01 +01:00
src_files.yml Rename zeroriscy to ibex 2019-04-26 15:05:01 +01:00

ibex: RISC-V Core

ibex is a small 2-stage RISC-V core derived from RI5CY.

ibex fully implements the RV32IMC instruction set and a minimal set of RISCV privileged specifications. ibex can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions. This configuration is called micro-riscy

The core was developed as part of the PULP platform for energy-efficient computing and is currently used as the control core for PULP and PULPino.

Documentation

A datasheet that explains the most important features of the core can be found in the doc folder.